DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim 8, 10-15, 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US Pub. 2010/0110772).
Regarding claims 8, and 17, Fig. 4 of Lee discloses an apparatus comprising:
a column select circuit [15] coupled to a complementary pair of bitlines [BLB, BL], the column select circuit including a pair of transistors [Q1, Q2] each coupled in series with a respective one of the complementary pair of bitlines [BLB, BL] and configured to provide a voltage on the respective one of the complementary pair of bitlines [BLB, BL] to a respective one of a complementary pair of local input/output (LIO) lines [LIOB, LIO] in response to a column select signal [CSL]; and
a LIO circuit [18] comprising a pair of p-type transistors [PM2, PM3] cross-coupled between the complementary pair of LIO lines [LIOB, LIO] and a pair of n-type transistors [MN1, MN2] cross-coupled between the complementary pair of LIO lines [LIOB, LIO], wherein the pair of p-type transistors [PM2, PM3] and the pair of n-type transistors [MN1, MN2] are configured to transition the complementary pair of LIO lines [LIOB, LIO] to complementary values based on values provided on the complementary pair of bitlines [BLB, BL].
Regarding claim 10, Fig. 4 and Fig. 6 of Lee discloses a read circuit [19, Fig. 4] coupled to one of the complementary pair of LIO lines [LIO, LIOB] and configured to, during a read operation, drive a main input/output (MIO) line [GIO, GIOB, Fig. 6] based on a value provided on the one of the complementary pair of LIO lines [LIO, LIOB, Fig. 6].
Regarding claims 11 and 18, Fig. 6 of Lee discloses wherein the read circuit comprises: a first n-type transistor [202] having a drain coupled to the MIO line [GIO] and a gate selectively coupled to the one of the complementary pair of LIO lines [LIOB] based on a read select signal [PLSAE]; and a second n-type transistor [201] configured to couple the gate of the n-type transistor to the one of the complementary pair of LIO lines [LIO] in response to the read select signal received at a gate of the second n-type transistor [201] being active.
Regarding claims 12 and 19, Fig. 6 of Lee discloses wherein the read circuit further comprises a third n-type transistor [203] configured to couple the gate of the n-type transistor to a reference voltage [ground] in response to the read select signal being inactive [PLSAE being high].
Regarding claim 13, Fig. 6 of Lee discloses wherein a source of the first n-type transistor [202] of the read circuit is coupled to the reference voltage [ground, through transistor 203].
Regarding claims 14 and 20, Fig. 4 of Lee discloses wherein the LIO circuit further comprises an equalization circuit [combination of PM4 and MN4] configured to couple the complementary pair of LIO lines [LIO, LIOB] together during an equalization phase of a read operation.
Regarding claim 15, Fig. 4 of Lee discloses an apparatus comprising:
a column select circuit [15] coupled to a complementary pair of bitlines [BLB, BL], the column select circuit including a pair of transistors [Q1, Q2] each coupled in series with a respective one of the complementary pair of bitlines [BLB, BL] and configured to provide a voltage on the respective one of the complementary pair of bitlines [BLB, BL] to a respective one of a complementary pair of local input/output (LIO) lines [LIOB, LIO] in response to a column select signal [CSL]; and
a LIO circuit [18] comprising a pair of transistors [PM2, PM3] cross-coupled between the complementary pair of LIO lines [LIOB, LIO], wherein the pair of transistors [PM2, PM3] is configured to transition the complementary pair of LIO lines [LIOB, LIO] to complementary values based on values provided on the complementary pair of bitlines [BLB, LB]; and
a read circuit [19] coupled to one of the complementary pair of LIO lines [LIOB, LIO] and configured to, during a read operation, drive a main input/output (MIO) line [GIO, GIOB] based on a value provided on the one of the complementary pair of LIO lines [LIOB, LIO], wherein the read circuit an n-type transistor [202, Fig. 6] having a drain coupled to the MIO line [GIO] and a gate selectively coupled to the one of the complementary pair of LIO lines [LIOB] based on a read select signal [PLSAE].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-7, 9, 16 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US Pub. 2010/0110772) in view of Kwak (US Pub. 2009/0086550).
Regarding claims 1, 9, and 16, Fig. 4 of Lee discloses an apparatus comprising:
a column select circuit [15] coupled to a complementary pair of bitlines [BLB, BL], the column select circuit including a pair of n-type transistors [Q1, Q2] each coupled in series with a respective one of the complementary pair of bitlines [BLB, BL, respectively] and configured to provide a voltage on the respective one of the complementary pair of bitlines [BLB, BL] to a respective one of a complementary pair of local input/output (LIO) lines [LIOB, LIO, respectively] in response to a column select signal [CSL]; and
a LIO circuit [18] comprising a pair of transistors [PM2, PM3] cross-coupled between the complementary pair of LIO lines [LIOB, LIO], wherein the pair of transistors is configured to transition the complementary pair of LIO lines [LIOB, LIO] to complementary values based on values provided on the complementary pair of bitlines [BLB, BL].
Lee discloses the column select circuit includes a pair of n-type transistors instead of p-type transistors.
However, Fig. 2A of Kwak discloses a memory circuit having a column select circuit having a pair of p-type transistors [the two transistors that are controlled by column signal YI].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Kwak’s memory device having column select circuit to the teachings of Lee’s memory circuit having column select circuit such that Lee memory device operates to activate with low signal according to Kwak’s teachings for the purpose of connecting the pair of bit lines to the pair of LIO lines when column select signal is low.
Regarding claim 2, Fig. 4 of Lee discloses wherein the pair of transistors of the LIO circuit are each p-type transistors [PM2, PM3], wherein the LIO circuit further comprises a pair of n-type transistors [MN1, MN2] cross-coupled between the complementary pair of LIO lines [LIO, LIOB], wherein the pair of n-type transistors is configured to transition the complementary pair of LIO lines [LIOB, LIO] to the complementary values based on the values provided on the complementary pair of bitlines [BLB, BL].
Regarding claim 3, Fig. 4 and Fig. 6 of Lee discloses a read circuit [19, Fig. 4] coupled to one of the complementary pair of LIO lines [LIO, LIOB] and configured to, during a read operation, drive a main input/output (MIO) line [GIO, GIOB, Fig. 6] based on a value provided on the one of the complementary pair of LIO lines [LIO, LIOB, Fig. 6].
Regarding claim 4, Fig. 6 of Lee discloses wherein the read circuit comprises an n-type transistor [202] having a drain coupled to the MIO line [GIO] and a gate selectively coupled to the one of the complementary pair of LIO lines [LIOB] based on a read select signal [PLSAE].
Regarding claim 5, Fig. 6 of Lee discloses wherein the read circuit further comprises a second n-type transistor [201] configured to couple the gate of the n-type transistor to the one of the complementary pair of LIO lines [LIO] in response to the read select signal [PLSAE] received at a gate of the second n-type transistor being active.
Regarding claim 6, Fig. 6 of Lee discloses wherein the read circuit further comprises a third n-type transistor [203] configured to couple the gate of the n-type transistor to a reference voltage [ground] in response to the read select signal being inactive [PLSAE being high].
Regarding claim 7, Fig. 4 of Lee discloses wherein the LIO circuit further comprises an equalization circuit [combination of PM4 and MN4] configured to couple the complementary pair of LIO lines [LIO, LIOB] together during an equalization phase of a read operation.
Conclusion
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825