Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This office action is in response to the amendments filed on 12/30/2025. New claims 6-11 have been added. Currently, claims 1-11 are pending.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim 6 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 6 is ambiguous; it appears the claim meant to be “the third conductive layer is directly on the second conductive layer, and the second conductive layer is directly on the second gate dielectric layer.” Appropriate correction or an explanation is needed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim 1 and 3-11 are rejected under 35 U.S.C. 103 as being unpatentable over Shao et al. (Pub. No. US 2021/0305251 A1) in view of Jang et al. (Pub. No. US 2016/0163708 A1), herein Jang.
Regarding claim 1, Shao discloses a semiconductor device comprising: a substrate 102 (Shao: paragraph [0015]) comprising a first region 107D and a second region 107C; a first gate structure152D in the first region (Shao: Figs. 79-80 and paragraphs [0047]-[0048]) and comprising a first gate dielectric layer 116 (Shao: Figs. 79-80 and paragraph [0028]), a first conductive layer 122 (Shao: Figs. 79-80 and paragraph [0035]), a second conductive layer 124 (Shao: Figs. 79-80 and paragraph [0039]), and a third conductive layer 129 (Shao: Figs. 79-80 and paragraph [0045]), stacked in sequence; and a second gate structure 152C in the second region and comprising a second gate dielectric layer 116, the second conductive layer 126, and the third conductive layer 129, stacked in sequence (Shao: Figs. 79-80 and paragraphs [0047]-[0048]), wherein the second gate dielectric layer 116 is positioned on at least a first surface and a second surface of the second conductive layer 124, and wherein a first transistor comprising the first gate structure and a second transistor comprising the second gate structure define respective p-type MOSFETs (SLVT-P & RVT-P; Shao: Figs. 79-80 and paragraphs [0017], [0046]).
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Shao does not specifically show the first gate dielectric layer and the first conductive layer comprise a first element, and wherein the second conductive layer and the second gate dielectric layer are free of the first element.
However, in the same field of endeavor, Jang discloses a semiconductor device comprising: a substrate comprising a first region “CNL” and a second region “CNH” (Jang: paragraphs [0104]-[0107], Any transistor/gate structure can be considered to be the first or second region as the current claim language does not specify the relationship between each two adjacent gate structures.); a first gate structure in the first region and comprising a first gate dielectric layer 134/136, a first conductive layer 144, a second conductive layer 142, and a third conductive layer 154, stacked in sequence (Jang: Fig. 13 and paragraph [0070]); and a second gate structure in the second region and comprising a second gate dielectric layer 132/136, the second conductive layer 142, and the third conductive layer 154, stacked in sequence (Jang: Fig. 13 and paragraph [0075]), wherein the first gate dielectric layer and the first conductive layer comprise a first element “La”/ “Sr” (Jang: Paragraph [0056] states “the high-k insulating layer 136a may be formed of at least one selected material selected from the group consisting of hafnium oxide (HfO), hafnium silicate (HfSiO), hafnium oxynitride (HfON), hafnium silicon oxynitride (HfSiON), lanthanum oxide (LaO), lanthanum oxide nitride (LaON), lanthanum aluminum oxide (LaAlO), zirconium oxide (ZrO), zirconium silicate (ZrSiO), zirconium oxynitride (ZrON), zirconium silicon oxynitride (ZrSiON), tantalum oxide (TaO), titanium oxide (TiO), barium strontium titanium oxide (BaSrTiO), barium titanium oxide (BaTiO), strontium titanium oxide (SrTiO), yttrium oxide (YO), aluminum oxide (AlO), aluminum oxide nitride (AlON), and lead scandium tantalum oxide (PbScTaO). For example, the high-k insulating layer 136a may be formed of HfO2, Al2O3, HfAlO3, Ta2O3, or TiO2.” Paragraph [0059] says “a second metal gate material layer 144a may be formed of a single layer of material or a composite of materials. For example, the second metal gate material layer 144a may be formed of La/TiN, Mg/TiN, Sr/TiN, LaO/TiN or LaON/TiN.”), and wherein the second conductive layer and the second gate dielectric layer are free of the first element (Jang: Paragraph [0057] states “for example, the first metal gate material layer 142a may be formed of TiN, TiN/TaN, Al2O3/TiN, Al/TiN, TiN/Al/TiN, TiN/TiON, Ta/TiN, or TaN/TiN, and TiN may be replaced with TaN, TaCN, TiCN, CoN, or CoCN.” And paragraph [0050] says “the first dielectric layer 132a may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or oxide/nitride/oxide (ONO).” Furthermore, according to MPEP § 2173.05(i), negative limitations such as “free of the first element” may be claimed as long as they are clear and supported by the specification. Negative limitations must have basis in the original disclosure.) to have higher degrees of integration and improved operating speeds (Jang: paragraphs [0004]- [0007]).
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Therefore, given the teachings of Jang, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying Shao in view of Jang by employing the first gate dielectric layer and the first conductive layer comprising a first element, and wherein the second conductive layer and the second gate dielectric layer are free of the first element.
Regarding claim 3, Shao in view of Jang teaches the semiconductor device according to claim 1, wherein the first gate structure further comprises a lower conductive layer disposed between the first gate dielectric layer and the first conductive layer (Paragraph [0059] of Jang states “metal gate material layer 144a may be formed of a single layer of material or a composite of materials. For example, the second metal gate material layer 144a may be formed of La/TiN, Mg/TiN, Sr/TiN, LaO/TiN or LaON/TiN. Therefore, Jang discloses the lower conductive layer disposed between the first gate dielectric layer and the first conductive layer 144.).
Regarding claim 4, Jang, in paragraph [0059] says “the second metal gate material layer 144a may be formed to a thickness of about 30 Å to about 60 Å” but does not specifically say “a thickness of the lower conductive layer is in a range of about 2 Å to about 10 Å”. However, the claimed thickness range is recognized as a result-effective variable, i.e., a variable which achieves a recognized result. Thicker gate metal has lower sheet resistance, so the gate can charge and discharge faster. Thinner gate metal has higher resistance, which slows down switching an worsens delay, especially for wide devices or at high frequencies. Gate metal thickness also affects the electromigration, reliability, capacitive coupling, threshold voltage variability, and manufacturing stress on the gate stack. Therefore, it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose the particular claimed temperature range because applicant has not disclosed that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another temperature range. The claim(s) is(are) obvious without showing that the claimed range(s) achieve unexpected results relative to the prior art range. See In re Aller, 105 USPQ 233 (CCPA 1955) and In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Huang, 40 USPQ2d 1685, 1688 (Fed. Cir. 1996) (claimed ranges of a result effective variable, which do not overlap the prior art ranges, are unpatentable unless they produce a new and unexpected result which is different in kind and not merely in degree from the results of the prior art). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art).
Regarding claim 5, Shao in view of Jang teaches the semiconductor device according to claim 1, wherein the second gate dielectric layer comprises a second element that is different from the first element, and wherein the first gate dielectric layer is free of the second element (Paragraph [0054] of Jang says the first gate dielectric layer 134 may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or ONO. And paragraph [0050] of Jang states the second gate dielectric layer 132 may be formed of, for example, silicon oxide, silicon nitride, silicon oxynitride, or oxide/nitride/oxide (ONO). In addition, paragraph [0056] of Jang says the dielectric layer 136 may be made of HfO2, Al2O3, HfAlO3, Ta2O3, or TiO2. Therefore, any combination can be chosen among these materials that meet the claimed limitation. One example would be, having SiO2 for the second gate dielectric layer 132 and having LaO for the first gate dielectric layer 136, which satisfies the claimed limitation “the second gate dielectric layer comprises a second element “Si” or “Nitrogen” that is different from the first element “La”, and wherein the first gate dielectric layer is free of the second element).
Regarding claim 6, Shao in view of Jang teaches the semiconductor device according to claim 1, wherein the second gate dielectric layer is directly on the second conductive layer, and the second conductive layer is directly on the third conductive layer (Shao: Figs. 79-80 and paragraphs [0047]-[0048]).
Regarding claim 7, Shao in view of Jang teaches the semiconductor device according to claim 1, wherein the second gate dielectric layer comprises at least one of hafnium (Hf), titanium (Ti), zirconium (Zr), or praseodymium (Pr) (Shao: Figs. 79-80 and paragraph [0028]).
Regarding claim 8, Shao in view of Jang teaches the semiconductor device according to claim 1, wherein a thickness of the second conductive layer is greater than a thickness of the first conductive layer (Shao: Figs. 79-80 and paragraph [0039]: “The third TiN layer 124 may be formed to any desired thickness, e.g., 1-30 nm, and it may be formed by performing any type of conformal deposition process, e.g., a conformal ALD process.”).
Regarding claim 9, Shao in view of Jang teaches the semiconductor device according to claim 1, wherein a thickness of the third conductive layer is greater than a thickness of the first conductive layer (Shao: Figs. 79-80 and paragraph [0039]; “The N-type work function adjusting material layer(s) 129 may be formed to any desired thickness, e.g., 5-50 nm, and it or they may be formed by performing any type of conformal deposition process, e.g., a conformal ALD process.”).
Regarding claim 10, Shao in view of Jang teaches the semiconductor device according to claim 1, wherein a material of the third conductive layer is the same as a material of the first conductive layer (Shao: Figs. 79-80 and paragraph [0039]; “The N-type work function adjusting material layer(s) 129 may be formed to any desired thickness, e.g., 5-50 nm, and it or they may be formed by performing any type of conformal deposition process, e.g., a conformal ALD process.”).
Regarding claim 11, Shao in view of Jang teaches the semiconductor device according to claim 1, wherein the first and second transistors have substantially same respective channel lengths (Shao: Figs. 79-80 and paragraphs [0047]-[0048]).
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Shao in view of Jang, as applied above, and further in view of Ando et al. (Pub. No. US 2017/0243789 A1, herein Ando).
Regarding claim 2, Jang does not specifically show the first element comprises at least one of aluminum (Al), tantalum (Ta), tungsten (W), manganese (Mn), chromium (Cr), ruthenium (Ru), platinum (Pt), gallium (Ga), germanium (Ge), or gold (Au).
However, in the same field of endeavor, Ando (in Fig. 6 and paragraphs [0047]), [0049]) teaches a CMOS structure, wherein the gate dielectric 502 is a high-k oxide such as, for example, hafnium dioxide, zirconium dioxide, aluminum oxide, titanium dioxide, lanthanum oxide, strontium titanium oxide, lanthanum aluminum oxide, yttrium oxide, and mixtures thereof, and the gate metal 602 may include layers of elemental aluminum or tungsten above the alloy layers.
Therefore, given the teachings of Ando, a person having ordinary skill in the art before the effective filing date of the claimed invention would have readily recognized the desirability and advantages of modifying the previous combination in view of Ando by employing the aluminum element, as the selection of a known material based on its suitability for its intended use supported a prima facie obviousness determination in Sincalir & Carroll Co. v. International Corp., 325 U.S. 327, 65 USPQ 297 (1945).
Response to Arguments
Applicant’s arguments with respect to claims 1-11 have been fully considered, but are found to be moot in view of the new grounds of rejection.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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March 17, 2026
/MALIHEH MALEK/
Primary Examiner, Art Unit 2813