Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the 20claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 4, 17 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi (US 2023/0301119, hereinafter Takahashi) in view of Lee (US 2022/0336533, hereinafter Lee).
With respect to claim 1, Takahashi discloses a vertical non-volatile memory device (Fig. 4 - Para 0020 –non-volatile memory device) comprising: a plurality of memory cell strings arranged two-dimensionally (Para 0023; 0031- plurality of memory strings), wherein each of the plurality of memory cell strings (Para 0023; 0031 – memory cell array) includes a channel layer (44 of Fig. 4 - Para 0064-0065) extending in a first direction (44 extends in vertical direction), a plurality of conductor layers (conductor layers 22 – Para 0053) and a plurality of spacers (insulator layers 32 – Para 0053) alternately arranged in the first direction (Para 0053-0054 – layers 22 & 32 are alternately arranged in vertical direction) and each extending in a second direction (layers 22 & 32 extend in horizontal direction), the second direction crossing the first direction (horizontal and direction crosses vertical direction), a gate insulating film (33) extending in the first direction (33 extends in vertical direction) and between the channel layer and the plurality of conductor layers (33 is between 44 and 22s), and a resistance change layer (42) extending in the first direction along a surface of the channel layer (42 extends in vertical direction), a material in the resistance change layer is capable of switching between a first state having a first threshold voltage and a second state having a second threshold voltage (Para 0089-0090; 0097 and 0099), and the second threshold voltage is greater than the first threshold voltage (Para 0089-0090).
Takahashi does not explicitly disclose that the conductor layers are gate electrodes.
In an analogous art, Lee discloses that the conductor layers are gate electrodes (Para 0077 and 0090 – conductor layers are gate electrode layers). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Takahashi’s method/system by having Lee’s disclosure in order to regulate current flow through the channel.
With respect to claim 4, Takahashi discloses wherein the non-volatile memory device is configured to perform a read operation that includes applying a read voltage between the first threshold voltage and the second threshold voltage to the resistance change layer (Para 0027; 0029; 0093 and 0100).
With respect to claim 17, Takahashi discloses wherein the resistance change layer has a property where, during switching between the first state and the second state, an element composition distribution in the first region and the second region is maintained constant (Para 0034; 0124 and 0127).
With respect to claim 20, Takahashi discloses an electronic device (Fig. 4 - Para 0020 –non-volatile memory device) comprising:
a processing circuitry (Para 0030); and
a vertical non-volatile memory device connected to the processing circuitry (Para 0020), the vertical non-voaltile memory device including a plurality of memory cell strings arranged two-dimensionally (Fig. 4), wherein each of the plurality of memory cell strings arranged two-dimensionally (Para 0023; 0031- plurality of memory strings), wherein each of the plurality of memory cell strings (Para 0023; 0031 – memory cell array) includes a channel layer (44 of Fig. 4 - Para 0064-0065) extending in a first direction (44 extends in vertical direction), a plurality of conductor layers (conductor layers 22 – Para 0053) and a plurality of spacers (insulator layers 32 – Para 0053) alternately arranged in the first direction (Para 0053-0054 – layers 22 & 32 are alternately arranged in vertical direction) and each extending in a second direction (layers 22 & 32 extend in horizontal direction), the second direction crossing the first direction (horizontal and direction crosses vertical direction), a gate insulating film (33) extending in the first direction (33 extends in vertical direction) and between the channel layer and the plurality of conductor layers (33 is between 44 and 22s), and a resistance change layer (42) extending in the first direction along a surface of the channel layer (42 extends in vertical direction), a material in the resistance change layer is capable of switching between a first state having a first threshold voltage and a second state having a second threshold voltage (Para 0089-0090; 0097 and 0099), and the second threshold voltage is greater than the first threshold voltage (Para 0089-0090).
Takahashi does not explicitly disclose that the conductor layers are gate electrodes.
In an analogous art, Lee discloses that the conductor layers are gate electrodes (Para 0077 and 0090 – conductor layers are gate electrode layers). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Takahashi’s method/system by having Lee’s disclosure in order to regulate current flow through the channel.
Claim 2 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi/Lee in view of Ikarashi et al. (US 2019/0296083, hereinafter Ikarashi).
With respect to claim 2, Takahashi/Lee discloses the vertical non-volatile memory device of claim 1.
Takahashi/Lee does not explicitly disclose wherein no current flows in the resistance change layer if the resistance change layer is in the first state and a voltage less than the first threshold voltage is applied to the resistance change layer, current flows in the resistance change layer if the resistance change layer is in the first state and a voltage greater than or equal to the first threshold voltage is applied to the resistance change layer, no current flows in the resistance change layer if the resistance change layer is in the second state and a voltage less than the second threshold voltage is applied to the resistance change layer, and current flows in the resistance change layer if the resistance change layer is in the second state and a voltage greater than or equal to the second threshold voltage is applied to the resistance change layer.
In an analogous art, Ikarashi discloses wherein no current flows in the resistance change layer if the resistance change layer is in the first state and a voltage less than the first threshold voltage is applied to the resistance change layer (Para 0085-0086), current flows in the resistance change layer if the resistance change layer is in the first state and a voltage greater than or equal to the first threshold voltage is applied to the resistance change layer (Para 0013-0014), no current flows in the resistance change layer if the resistance change layer is in the second state and a voltage less than the second threshold voltage is applied to the resistance change layer (Para 0085-0086; 0105), and current flows in the resistance change layer if the resistance change layer is in the second state and a voltage greater than or equal to the second threshold voltage is applied to the resistance change layer (Para 0038-0039; and 0086). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Takahashi/Lee’s method/system by having Ikarashi’s disclosure in order to suppress occurance fo a sneak current when writing or reading information in a memory device.
Claims 5-8 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi/Lee in view of Cheng et al. (US 10,374,009, hereinafter Cheng).
With respect to claim 5, Takahashi/Lee discloses the vertical non-volatile memory device of claim 1.
Takahashi/Lee does not explicitly disclose wherein the resistance change layer has a single layer structure including at least one amorphous multi-component chalcogenide material among GeAsSe, GeAsSeln, GeAsSeSIn, GeAsSeSb, GeAsSeSbln, GeAsSeTe, GeAsSeTeln, GeAsSeAl, GeAsSeAlln, GeSbSe, GeSbSeln, GeSbSeN, GeSbSeNIn, CTe, GeCTe, NGeCTe, BTe, SiTe, GeAsTe, GeSbSe, and GeSbSeN.
In an analogous art, Cheng discloses wherein the resistance change layer has a single layer structure including at least one amorphous multi-component chalcogenide material among GeAsSe, GeAsSeln, GeAsSeSIn, GeAsSeSb, GeAsSeSbln, GeAsSeTe, GeAsSeTeln, GeAsSeAl, GeAsSeAlln, GeSbSe, GeSbSeln, GeSbSeN, GeSbSeNIn, CTe, GeCTe, NGeCTe, BTe, SiTe, GeAsTe, GeSbSe, and GeSbSeN (Col. 5; lines 50-67; Col. 6; lines 50-60 – AsSeGe). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Takahashi/Lee’s method/system by having Cheng’s disclosure in order to improve the storage capabilities of a memory device.
With respect to claim 6, Takahashi/Lee/Cheng discloses the vertical non-volatile memory device of claim 5.
Takahashi/Lee does not explicitly disclose wherein a ratio of germanium (Ge) in the resistance change layer is 10 at% to 30 at%.
In an analogous art, Cheng discloses wherein a ratio of germanium (Ge) in the resistance change layer is 10 at% to 30 at% (Col. 4 – lines 5-10 – Ge in a range of 10 at% to 25 at %). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Takahashi/Lee’s method/system by having Cheng’s disclosure in order to improve the storage capabilities of a memory device.
With respect to claim 7, Takahashi/Lee/Cheng discloses the vertical non-volatile memory device of claim 5.
Takahashi/Lee does not explicitly disclose wherein a ratio of arsenic (As) in the resistance change layer is 10 at% to 50 at%.
In an analogous art, Cheng discloses wherein a ratio of arsenic (As) in the resistance change layer is 10 at% to 50 at% (Col. 4, lines 5-10 – As in a range of 15 at% to 46 at%). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Takahashi/Lee’s method/system by having Cheng’s disclosure in order to improve the storage capabilities of a memory device.
With respect to claim 8, Takahashi/Lee/Cheng discloses the vertical non-volatile memory device of claim 5.
Takahashi/Lee does not explicitly disclose wherein a ratio of selenium (Se) in the resistance change layer is 40 at% to 80 at%.
In analogous art, Cheng discloses wherein a ratio of selenium (Se) in the resistance change layer is 40 at% to 80 at% (Col. 4, lines 5-10 – 60 at%). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Takahashi/Lee’s method/system by having Cheng’s disclosure in order to improve the storage capabilities of a memory device.
With respect to claim 18, Takahashi/Lee discloses the vertical non-volatile memory device of claim 1.
Takahashi/Lee does not explicitly disclose wherein a thickness of the resistance change layer in the second direction is 5 nm to 100 nm.
In an analogous art, Cheng discloses wherein a thickness of the resistance change layer in the second direction is 5 nm to 100 nm (Col. 5; lines 42-45). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Takahashi/Lee’s method/system by having Cheng’s disclosure in order to improve the storage capabilities of a memory device.
Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over
Takahashi/Lee/Cheng in view of Cheng et al. (US 2021/0210554, hereinafter Cheng II).
With respect to claim 9, Takahashi/Lee/Cheng does not explicitly disclose
wherein a ratio of indium (In) in the resistance change layer is 1 at% to 10 at%.
In an analogous art, Cheng II discloses wherein a ratio of indium (In) in the resistance change layer is 1 at% to 10 at% (Para 0006; and 0023). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Takahashi/Lee/Cheng’s method/system by having Cheng II’s disclosure in order to have improved yield and reduced cycling degradation.
Claims 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Takahashi/Lee in view of Kim et al. (US 2022/0020818, hereinafter Kim).
With respect to claim 10, Takahashi/Lee discloses the vertical non-volatile memory device of claim 1.
Takahashi/Lee does not explicitly disclose wherein the resistance change layer comprises a plurality of driving regions and a plurality of pristine-state regions alternately arranged in the first direction.
In an analogous art, Kim discloses wherein the resistance change layer comprises a plurality of driving regions and a plurality of pristine-state regions alternately arranged in the first direction (Para 0126-0127 – resistance change layer 523 comprises of 523a and 523b). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Takahashi/Lee/Cheng’s method/system by having Kim’s disclosure in order to have improved yield and reduced cycling degradation.
With respect to claim 11, Takahashi/Lee/Kim discloses the vertical non-volatile memory device of claim 10.
Takahashi/Lee does not explicitly disclose wherein each of the plurality of driving regions faces a corresponding gate electrode of the plurality of gate electrodes in the second direction, and each of the plurality of pristine-state regions faces a corresponding spacer of the plurality of spacers in the second direction.
In an analogous art, Kim discloses wherein each of the plurality of driving regions faces a corresponding gate electrode of the plurality of gate electrodes in the second direction (Para 0123 and 0127 - 523b corresponding to non-selected memory cell), and each of the plurality of pristine-state regions faces a corresponding spacer of the plurality of spacers in the second direction (Para 0142 – 523a corresponding to selected memory cell). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Takahashi/Lee/Cheng’s method/system by having Kim’s disclosure in order to have improved yield and reduced cycling degradation.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Takahashi/Lee in view of Maehara (US 2023/0335441, hereinafter Maehara).
With respect to claim 19, Takahashi/Lee discloses the vertical non-volatile memory device of claim 1.
Takahashi discloses wherein each of the plurality of memory cell strings further comprises a barrier layer (43 of Fig. 4) extending in the first direction between the channel layer and the resistance change layer (Fig. 4).
Takahashi/Lee does not explicitly disclose that the barrier layer comprises a carbon-based non-conductor or a nitrogen- based non-conductor, and a thickness of the barrier layer in the second direction is greater than 0 nm and less than or equal to 10 nm.
In an analogous art, Maehara discloses that the barrier layer comprises a carbon-based non-conductor or a nitrogen- based non-conductor (Para 0066 – SiCN), and a thickness of the barrier layer in the second direction is greater than 0 nm and less than or equal to 10 nm (Para 0066 – 10 nm). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Takahashi/Lee’s method/system by having Maehara’s disclosure in order to improve the storage capabilities of a memory device.
Allowable Subject Matter
Claims 3, 12 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 14-16 are objected because of their dependency claim 13.
With respect to claim 3, none of the prior art on record disclose or render obvious the claimed limitations including “the resistance change layer is configured to switch from the first state to the second state in response to the resistance change layer being in the first state while a sufficient negative (-) bias voltage is applied to the resistance change layer, and the resistance change layer is configured to switch from the first state to the second state in response to the resistance change layer being in the second state while a positive (+) bias voltage greater than the second threshold voltage is applied to the resistance change layer.” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
With respect to claim 12, none of the prior art on record disclose or render obvious the claimed limitations including “in response to a voltage greater than or equal to the first threshold voltage being applied to the resistance change layer, a resistance of the plurality of pristine- state regions is greater than a resistance of the plurality of driving regions” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
With respect to claim 13, none of the prior art on record disclose or render obvious the claimed limitations including “each of the plurality of driving regions comprises a first region and a second region having different densities of activated traps” when considered as a whole along with all of the limitations of the base claim and any intervening claims.
Conclusion
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/MOHAMMAD M CHOUDHRY/Primary Examiner, Art Unit 2899
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