Prosecution Insights
Last updated: July 17, 2026
Application No. 18/743,774

DEVICE OF MASS TRANSFERRING CHIPS

Non-Final OA §102§103
Filed
Jun 14, 2024
Priority
May 05, 2021 — TW 110116277 +1 more
Examiner
ROMANO, ASHLEY K
Art Unit
Tech Center
Assignee
AUO Corporation
OA Round
1 (Non-Final)
79%
Grant Probability
Favorable
1-2
OA Rounds
5m
Est. Remaining
86%
With Interview

Examiner Intelligence

Grants 79% — above average
79%
Career Allowance Rate
389 granted / 495 resolved
+18.6% vs TC avg
Moderate +7% lift
Without
With
+7.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
18 currently pending
Career history
516
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
77.6%
+37.6% vs TC avg
§102
15.0%
-25.0% vs TC avg
§112
4.3%
-35.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 495 resolved cases

Office Action

§102 §103
Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-4, 6-9, 11-15 rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hu (US Pub App 2014/0159065). Regarding claim 1, Hu discloses a device of mass transferring chips (Abstract), comprising: a first substrate (200, Fig.6D), comprising a chip-connecting area (204, Fig.6D) configured to connect a chip (475); a second substrate (300, Fig.6D), comprising a support layer (300) and a first adhesive layer (302), wherein the chip (475, Fig.6D) is between the first substrate (200, Fig.6D) and the second substrate (300, Fig.6D), and the first adhesive layer (302) comprises: a first surface (top surface of 302) with a chip-receiving area configured to attach the chip from the first substrate; a second surface (bottom surface of 302) opposite to the first surface and in contact with a first side of the support layer; and a patterned recess (between each of 302), disposed on the first surface and spaced apart from the chip-receiving area (Fig.6D). Regarding claim 2, Hu further discloses wherein the patterned recess (between each of 302) comprises a trench laterally extending to a side surface of the first adhesive layer (Fig.6D). Regarding claim 3, Hu further discloses wherein a depth of the trench is from about 20% to about 80% of a thickness of the first adhesive layer (Fig.6D). Regarding claim 4, Hu further discloses wherein the patterned recess comprises a first patterned through hole penetrating from the first surface to the second surface (between each of 302). Regarding claim 6, Hu further discloses a second adhesive layer disposed on a second side of the support layer and physically contacting the support layer (Fig.1D). Regarding claim 7, Hu further discloses wherein a thickness of the second adhesive layer is greater than a thickness of the first adhesive layer by about 20% to about 50% of the thickness of the first adhesive layer (Fig.1D). Regarding claim 8, Hu further discloses a laser source configured to provide a laser, wherein a first absorption of the laser by the first adhesive layer is different from a second absorption of the laser by the second adhesive layer (Para.41). Regarding claim 9, Hu further discloses wherein the laser is absorbed by the first adhesive layer and passes through the second adhesive layer (Para.41). Regarding claim 11, Hu further discloses wherein the first adhesive layer has a first portion below the chip-receiving area and a second portion below the patterned recess, and a thickness of the first portion of the first adhesive layer is thicker than a thickness of the second portion of the first adhesive layer (Para.39). Regarding claim 12, Hu further discloses wherein the first substrate comprises a recess, wherein a projection of the recess on the first surface is spaced apart from the chip-connecting area (Fig.6D). Regarding claim 13, Hu further discloses wherein the first substrate comprises a through hole (207) disposed spaced apart from the chip-connecting area (Fig.6D). Regarding claim 14, Hu further discloses wherein the through hole of the first substrate aligns with the patterned recess of the second substrate (Fig.6D). Regarding claim 15, Hu further discloses wherein the patterned recess comprises a plurality of line structures which cross each other (Para.58). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim 10 rejected under 35 U.S.C. 103 as being unpatentable over Hu (US Pub App 2014/0159065) in view of Gardner (CN 107210293). Regarding claim 10, Hu does not further specifically disclose wherein a wavelength of the laser is about 355 nanometers. Gardner teaches an LED array on backplane and manufacturing method thereof wherein a wavelength of the laser is about 355 nanometers (10-400nm) (Para.4). It would have been obvious to one of ordinary skill in the art at the time the application was filed to have modified Hu in view of Gardner to have a wavelength of the laser be about 355 nanometers in order to use light energy of the ultraviolet range. Allowable Subject Matter Claims 5, 16-18 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance: The prior art of record fails to disclose or render obvious the claimed invention as set forth in claim 5 and subsequent dependent claims. The prior art of record does not disclose or render obvious a second patterned through hole positioned in alignment with the first patterned through hole. The prior art of record fails to disclose or render obvious the claimed invention as set forth in claim 16 and subsequent dependent claims. The prior art of record does not disclose or render obvious the patterned recess comprises a scattered pattern and a plurality of line structures connecting the scattered pattern to a side surface of the first adhesive layer. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Hanajima, Li, Xie, Itou and Achi further disclose elements of a device of mass transferring chips. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ASHLEY K ROMANO whose telephone number is (571)272-9318. The examiner can normally be reached Monday - Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Saul Rodriguez can be reached on 571-272-7097. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SAUL RODRIGUEZ/Supervisory Patent Examiner, Art Unit 3652 /ASHLEY K ROMANO/Examiner, Art Unit 3652
Read full office action

Prosecution Timeline

Jun 14, 2024
Application Filed
Jun 22, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
79%
Grant Probability
86%
With Interview (+7.4%)
2y 6m (~5m remaining)
Median Time to Grant
Low
PTA Risk
Based on 495 resolved cases by this examiner. Grant probability derived from career allowance rate.

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