DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-17 and 19-20 are rejected under 35 U.S.C. 102(a)(2) as anticipated by or, in the alternative, under 35 U.S.C. 103 as obvious over Lee et al. (US Pub. 2023/0410887).
Regarding claim 1, Fig. 1 of Lee discloses a memory core circuit comprising:
a memory cell array [20] including a plurality of sub cell arrays [22 and 26] arranged in a matrix, the matrix including a plurality of array rows and a plurality of array columns [Fig. 1 of Lee shows sub memory arrays arrange in one row and two columns of arrays. However, it is inherent or at least obvious that a memory device can have more row and column of memory arrays]; and
a core control circuit [28] including a plurality of sub peripheral circuits [34 and 46] arranged in the matrix including the plurality of array rows and the plurality of array columns [Fig. 1 of Lee shows the sub peripheral circuits arranges in one row and two columns. However, it is inherent or at least obvious that a memory device can have more row and column of sub peripheral circuit], wherein each sub peripheral circuit [34 and 46] is respectively under each sub cell array [22 and 26],
wherein each sub cell array includes:
a plurality of memory cells [528 in Fig. 9] respectively connected to a plurality of wordlines [536a to 536d, Fig. 9] and a plurality of bitlines [520a to 520d, Fig. 9], wherein the plurality of wordlines extend in a row direction and are arranged in a column direction [clearly shows in Fig. 9, paragraph 0052], wherein the plurality of bitlines extend in the column direction and are arranged in the row direction [clearly shows in Fig. 9, and as discloses in paragraph 0052], wherein
each sub peripheral circuit [34] is divided into a first column edge region [36], a second column edge region [44] and a central region [40], the first column edge region [36] and the second column edge region [44] corresponding to first and second end portions of each sub peripheral circuit [as clearly shows in Fig. 1] in the column direction, and the central region [40] is between the first column edge region [36] and the second column edge region [44],
a sense amplifier region [36] including a plurality of bitline sense amplifiers [SA] that respectively are configured to sense voltages of the plurality of bitlines is arranged in at least one of the first column edge region [SA is arranged in first column edge region 36] and the second column edge region, and
a wordline driver region [40] including a plurality of sub wordline drivers [WL Driver] that respectively are configured to drive the plurality of wordlines is arranged in the central region.
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Regarding claim 2, Fig. 6 of Lee discloses wherein, with respect to each sub peripheral circuit [346], the central region [360] is divided [as shows in Fig. 6, central region 360 comprises plurality of wordline drivers, which can be divided into two or more regions] into a first sub central region [C1] and a second sub central region [C2] in the row direction, one of the first sub central region and the second sub central region corresponds to the wordline driver region [Wordline Driver], and another of the first sub central region and the second sub central region corresponds to a rest region including other than the plurality of bitline sense amplifiers and the plurality of sub wordline drivers.
Regarding claim 3, Fig. 5 of Lee discloses wherein the core control circuit has a shift structure such that, with respect to a first sub peripheral circuit [304 and a second sub peripheral circuit [308] that are adjacent to each other in the row direction, the rest circuit region of the first sub peripheral circuit [314] is adjacent in the row direction to the wordline driver region [326] of the second sub peripheral circuit [308].
Regarding claim 4, Fig. 1 and Fig. 5 of Lee disclose wherein the core control circuit has a mirror structure such that, with respect to a first sub peripheral circuit [34] and a second sub peripheral circuit [46] that are adjacent to each other in the row direction, either the rest circuit region of the first sub peripheral circuit is adjacent in the row direction to the rest circuit region of the second sub peripheral circuit [as shows in Fig. 5], or the sense amplifier region [36] of the first sub peripheral circuit [34] is adjacent in the row direction to the sense amplifier region [48] of the second sub peripheral circuit [46].
Regarding claim 5, Fig. 6 of Lee discloses wherein, with respect to each sub peripheral circuit, two end portions [C1 and C2] in the row direction of the central region [360] corresponds to the wordline driver region [S/D] in which the plurality of sub wordline drivers are distributed and disposed, and a region [CM] between the two end portions [C1 and C2] of the central region corresponds to a rest region including remaining circuits excluding the plurality of bitline sense amplifiers and the plurality of sub wordline drivers.
Regarding claim 6, Fig. 1 of Lee discloses wherein, with respect to a first sub peripheral circuit [34] and a second sub peripheral circuit [46] adjacent to each other in the row direction, the wordline driver region [40] of the first sub peripheral circuit [34] is connected to odd-numbered wordlines [WL Driver connects to both even and odd wordlines, and thus inherently connected to odd wordlines], and the wordline driver region [52] of the second sub peripheral circuit [46] is connected to even-numbered wordlines [since WL Driver 52 connects to both even and odd wordlines, it inherently connect to even-numbered wordlines].
Regarding claim 7, Fig. 31 of Lee discloses wherein the wordline driver region [WL Driver] of each sub peripheral circuit includes: a first wordline driver region [1250] connected to first wordlines [one or more wordlines WL1 to WLN] above the central region in a vertical direction [Y Direction] respectively perpendicular to the row direction [X direction] and the column direction; a second wordline driver region [1252] connected to second wordlines [one or more wordlines WL1 to WLN] above the first column edge region in the vertical direction [Y direction]; and a third wordline driver region [1254] connected to third wordlines above the second column edge region in the vertical direction [Y direction].
Regarding claim 8, Fig. 31 of Lee discloses column conduction paths [1262a to 1262d, 1266a to 1266d] extending in the column direction to connect the second wordlines [1260a to 1260d] to the sub wordline drivers [1252] in the second wordline driver region [1252] and connect the third wordlines [1264a to 1264d] to the sub wordline drivers in the third wordline driver region [1254].
Regarding claim 9, Fig. 1 of Lee discloses wherein each sub peripheral circuit includes 2N bitline sense amplifiers [34] connected to 2N bitlines [30] among 4N bitlines [as shows in Fig. 9, each sense amplifier can connects to two different bit lines, therefore, it is obvious or inherent that if there are 2N amplifiers, the number of bit lines is 4N] corresponding to each sub peripheral circuit where N is a natural number, such that N bitline sense amplifiers [half of amplifiers of 34 on top half of section 36] among the 2N bitline sense amplifiers are in the first column edge region of each sub peripheral circuit and N other bitline sense amplifiers among the 2N bitline sense amplifiers are in the second column edge region of each sub peripheral circuit [the other half of amplifiers 34 are on the bottom half of section 36].
Regarding claims 10 and 14, Fig. 9 of Lee discloses wherein the 2N other bitlines among the 4N bitlines are connected, as complementary bitlines [one of bit line in arrays 510 and 512 can be complementary bit line], to bitline sense amplifiers included in two sub peripheral circuits adjacent in the column direction to each sub peripheral circuit [as shows in Fig. 5].
Regarding claims 11, 12, and 16, Fig.1 and Fig. 5 of Lee discloses wherein each odd-numbered sub peripheral circuit [24, Fig. 1] having sense amplifier [34]. Also, as shows in fig. 1 and Fig. 5 of Lee, sense amplifiers circuit can be arranged at different regions of sub peripheral circuit. Lee does not specifically disclose one sub-peripheral circuit does not have sense amplifier and another sub peripheral circuit have 4N bitline sense amplifiers. It would have been obvious to one of ordinary skill in the art at the time the invention was made to arrange double number of sense amplifier in one sub peripheral circuit and arrange no amplifier in another sub peripheral circuit, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding claim 13, Fig. 1 of Lee discloses wherein each sub peripheral circuit includes 2N bitline sense amplifiers [34] connected to 2N bitlines [30] among 4N bitlines [as shows in Fig. 9, each sense amplifier can connects to two different bit lines, therefore, it is obvious or inherent that if there are 2N amplifiers, the number of bit lines is 4N] corresponding to each sub peripheral circuit where N is a natural number, such that All of the 2N bitline sense amplifiers [34] are in the first column edge region [36] of each sub peripheral circuit, or all of the 2N bitline sense amplifiers are in the second column edge region of each sub peripheral circuit.
Regarding claim 15, Fig. 1 and Fig. 5 of Lee discloses wherein, with respect to a first sub peripheral circuit [24, Fig. 1] and a second sub peripheral circuit [28, Fig. 1] that are adjacent to each other in the row direction [X direction]. Fig. 1 and Fig. 5 of Lee shows that WL driver can be arranged in different regions of the sub peripheral circuit, but does not specifically shows the first sub peripheral circuit does not include the wordline driver region and the second sub peripheral circuit includes the wordline driver region corresponding to the central region. It would have been obvious to one of ordinary skill in the art at the time the invention was made to arrange WL driver in one of the sub peripheral circuit and not arrange WL driver in another sub peripheral circuit, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding claims 17, Fig. 1 and Fig. 6 of Lee shows what WL driver and sense amplifier can be arranged in different regions of sub peripheral circuits, but does not specifically shows the first sub peripheral circuit does not include the sense amplifier region and the wordline driver region and the second sub peripheral circuit includes a first sense amplifier region corresponding to the first column edge region, a second sense amplifier region corresponding to the second column edge region and the wordline driver region corresponding to the central region. However, it would have been obvious to one of ordinary skill in the art at the time the invention was made to arrange WL driver and sense amplifier in one of the sub peripheral circuit and not arrange WL driver and sense amplifier in another sub peripheral circuit, since it has been held that rearranging parts of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70.
Regarding claims 19 and 20, Fig. 1 of Lee discloses a memory core circuit comprising:
a memory cell array including a plurality of sub cell arrays [22 and 26] arranged in a matrix including a plurality of array rows and a plurality of array columns [Fig. 1 of Lee shows sub memory arrays arrange in one row and two columns of arrays. However, it is inherent or at least obvious that a memory device can have more row and column of memory arrays]; and
a core control circuit [28] including a plurality of sub peripheral circuits [34 and 46] arranged in a matrix including the plurality of array rows and the plurality of array columns [Fig. 1 of Lee shows the sub peripheral circuits arranges in one row and two columns. However, it is inherent or at least obvious that a memory device can have more row and column of sub peripheral circuit], wherein each sub peripheral circuit [34 and 46] is respectively under each sub cell array [22 and 26],
wherein each sub cell array includes:
a plurality of dynamic random access memory (DRAM) cells [paragraph 0052] respectively connected to a plurality of wordlines [536a to 536d, Fig. 9] and a plurality of bitlines [520a to 520d, Fig. 9], wherein the plurality of wordlines extend in a row direction and is arranged in a column direction [as clearly shows in Fig. 9], wherein the plurality of bitlines extend in the column direction and are arranged in the row direction [clearly shows in Fig. 9],
wherein each sub peripheral circuit [34 and 46] is divided into a first column edge region [36], a second column edge region [44] and a central region [40], the first column edge region [36] and the second column edge region [44] correspond to first and second end portions [clearly shows in Fig. 1] of each sub peripheral circuit in the column direction, the central region [40] is between the first column edge region [36] and the second column edge region [44], and the central region is divided into a first sub central region and a second sub central region in the row direction [as shows in Fig. 6, the central region 360 comprises plurality of wordline drivers (paragraph 0099). The central region 360 can be divided into two sub central region, each comprises plurality of word line drivers]
wherein a sense amplifier region [36] including a plurality of bitline sense amplifiers [SA] configured to respectively sense voltages of the plurality of bitlines [520a to 520d, Fig. 9] is distributed and arranged in the first column edge region [36] and the second column edge region, and
wherein a wordline driver region [40] including a plurality of sub wordline drivers [WL Driver] configured to respectively drive the plurality of wordlines is arranged in one of the first sub central region and the second sub central region [WL driver inherently drive plurality of wordlines].
Claim 18 is rejected under 35 U.S.C. 103 as being unpatentable over Lee et al. (US Pub. 2023/0410887) in view of Lee et al. (US Pub. 2022/0246180).
Regarding claim 18, Lee discloses all claimed invention, but does not specifically disclose wherein each memory cell includes: a vertical channel transistor; and a memory unit on the vertical channel transistor. However, Fig. 4 of Lee ‘180 discloses a memory device having each memory cell includes: a vertical channel transistor; and a memory unit on the vertical channel transistor [paragraph 0122].
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to apply the teachings of Lee ‘180’s memory cell having vertical channel to the teachings of Lee ‘887’s memory having transistor such that Lee ‘887 can stack in three dimensions according to Lee ‘180’s teachings for the purpose of reducing chip space.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANTHAN T TRAN whose telephone number is (571)272-8709. The examiner can normally be reached MON-FRI, 9AM-5:00PM.
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/ANTHAN TRAN/Primary Examiner, Art Unit 2825