DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
As per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
In responding to this Office action, the applicant is requested to include specific references (figures, paragraphs, lines, etc.) to the drawings/specification of the present application and/or the cited prior arts that clearly support any amendments/arguments presented in the response, to facilitate consideration of the amendments/arguments.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 102(a)(2) as being anticipated by US 2023/0056107 A1 to Shigekazu Yamada (hereafter Yamada).
Regarding Independent Claim 1, Yamada discloses a method of operating a memory device (Disclosing the following circuitry in a memory circuit: Yamada, ¶[0016]), comprising:
in a first charge stage (A two-stage charging sequence: Yamada, Figure 7D),
charging a first sensing node (Charging a first node: Yamada, Figure 7D)
to a first voltage (To first voltage Vinit: Yamada, Figure 7D)
through a first charge circuit (Charging to Vinit through first charge circuit including transistors 802 and 804: Yamada, Figure 9B),
wherein the memory device comprises
the first charge circuit and a second charge circuit (First charge circuit 804 and second charge circuit 806 & 808: Yamada, Figure 10B)
coupled to the first sensing node along with the first charge circuit (First and second charge circuit coupled to the sense node: Yamada, Figure 10B); and
in a second charge stage (A two-stage charging sequence: Yamada, Figure 7D),
charging the first sensing node and a bit line coupled to the first sensing node (Charging the first node and bitline BL_H: Yamada, Figure 7D)
to a second voltage (To second voltage Vx”: Yamada, Figure 7D)
through the second charge circuit (Increasing voltage through second charge circuit 806 & 808: Yamada, Figure 10B),
wherein the second voltage is higher than the first voltage (Second voltage Vx” being expressly larger than first voltage by relationship Vx” = Vinit + Vx: Yamada, Figure 7D).
Regarding Claim 2 and the substantially similar limitations of Claim 10, Yamada discloses the method of claim 1, wherein the charging the first sensing node to the first voltage through the first charge circuit comprises:
in the first charge stage (During the first charging stage: Yamada, ¶[0091]), applying a third voltage to a gate terminal of a clamp transistor to turn on the clamp transistor (Applying a voltage to the clamp transistor: Yamada, ¶[0091]),
wherein the first charge circuit comprises the clamp transistor connected to a power terminal and the first sensing node (The first charge circuit 804 connected between a power terminal and the sense node: Yamada, Figure 9B).
Regarding Claim 3 and the substantially similar limitations of Claim 11, Yamada discloses the method of claim 2, wherein the charging the first sensing node to the second voltage through the second charge circuit comprises:
in the second charge stage (During the second charging stage: Yamada, ¶[0100]),
applying a first pass voltage to a gate terminal of a first transistor to turn on the first transistor, and applying a second pass voltage to a gate terminal of a second transistor to turn on the second transistor (Applying pass voltages to first transistor 806 and second transistor 808: Yamada, ¶[0103] and Figure 10B); and
wherein the second charge circuit comprises the first transistor connected to the power terminal and a second sensing node (Transistors 806 & 808 connected between a power terminal and the sense node: Yamada, Figure 10B); and
the second transistor connected to the first sensing node and the second sensing node (The second transistor connected to the first sensing node and second sensing node: Yamada, Figure 10B; Note: under a broadest reasonable interpretation, ‘connected’ does not require direct connection and may include intervening circuitry).
Regarding Claim 4 and the substantially similar limitations of Claims 12 and 20, Yamada discloses the method of claim 3, further comprising:
in the first charge stage (During the first stage: Yamada, ¶[0091]),
applying the second pass voltage to the gate terminal of the second transistor to turn on the second transistor (Applying a pass voltage to transistor 808 during the first stage: Yamada, Figure 9B), and
charging the second sensing node to the first voltage (Charging the node to Vinit: Yamada, Figure 9B); and
in the second charge stage (During a second charge stage: Yamada, ¶[0100]),
charging the second sensing node from the first voltage to the second voltage (Charging the second node from Vinit to Vx”: Yamada, Figure 10B).
Regarding Claim 5 and the substantially similar limitations of Claim 13, Yamada discloses the method of claim 3, further comprising:
in the first charge stage (During the first charge stage: Yamada, ¶[0091]),
applying a fourth voltage to the gate terminal of the first transistor (Applying voltage 0V to gate terminal of transistor 806: Yamada, Figure 9B) to turn off the first transistor (Turning off transistor 806: Yamada, Figure 9B).
Regarding Claim 6 and the substantially similar limitations of Claim 15, Yamada discloses the method of claim 3, further comprising:
in the first charge stage (During first stage: Yamada, Figure 9B) and the second charge stage (During second stage: Yamada, Figure 10B),
applying a third pass voltage to a gate terminal of a third transistor to turn on the third transistor (Applying a pass voltage to transistor 804: Yamada, Figures 9B and 10B),
wherein the first charge circuit comprises the third transistor connected to the power terminal and the first transistor (Wherein transistor 804 is connected to the power terminal and the first transistor: Yamada, Figure 9B).
Regarding Claim 7 and the substantially similar limitations of Claim 15, Yamada discloses the method of claim 2, further comprising:
in the second charge stage (During second stage: Yamada, Figure 10B),
continuing to apply the third voltage to the gate terminal of the clamp transistor (Continuing to apply the pass voltage to the gate of transistor 804: Yamada, Figure 10B).
Regarding Claim 8, Yamada discloses the method of claim 1, wherein the second charge circuit comprises:
a fourth transistor connected with the first sensing node (Fourth transistor 213: Yamada, Figure 2); and
a fifth transistor connected with the bit line and the fourth transistor (Fifth transistor 263 connected between the fourth transistor and the bitline: Yamada, Figure 2), and
the method further comprising:
in the first charge stage and the second charge stage, applying a ramp voltage to a gate terminal of the fourth transistor until the ramp voltage rises to a fourth pass voltage (Applying a ramp voltage until passing a select pass voltage: Yamada, Figure 6); and
in the first charge stage and the second charge stage,
applying a fifth pass voltage to a gate terminal of the fifth transistor to turn on the fifth transistor (Applying a pass voltage to the fifth transistor 263: Yamada, ¶[0037]), wherein
the second charge circuit comprises
the fourth transistor connected to the first sensing node (Fourth transistor 213 connected to the sense node: Yamada, Figure 2; Note: under a broadest reasonable interpretation, ‘connected’ does not require direct connection and may include intervening circuitry); and
the fifth transistor connected to the bit line and the fourth transistor (Fifth transistor 263 connected to bit line and fourth transistor: Yamada, Figure 2).
Regarding Independent Claim 9, Yamada discloses a memory device, comprising:
a memory array (A memory device including a memory array: Yamada, ¶[0016]); and
a page buffer circuit coupled to a bit line in the memory array (A page buffer coupled to the memory array: Yamada, ¶[0024]), wherein the page buffer circuit comprises:
a first charge circuit (First charge circuit including transistor 804: Yamada, Figure 9B),
wherein a first terminal and a second terminal of the first charge circuit are connected to a power terminal and a first sensing node respectively (The first charge circuit connecting a power terminal and a first sensing node: Yamada, Figure 9B), and
the first charge circuit is configured to:
in a first charge stage, charge the first sensing node to a first voltage (Charging to Vinit through first charge circuit including transistors 802 and 804: Yamada, Figure 9B); and
a second charge circuit (A second charge circuit including transistors 806 & 808: Yamada, Figure 10B)
coupled to the first sensing node along with the first charge circuit (The second charge circuit connected a first node along with the first charge circuit: Yamada, Figure 10B),
wherein a first terminal and a second terminal of the second charge circuit are connected to the power terminal and the bit line respectively (The second charge circuit connecting the bitline and power terminal: Yamada, Figure 10B), and the second charge circuit is configured to:
in a second charge stage (During a second charging stage: Yamada, ¶[0100]),
charge the first sensing node and the bit line (Charging the first node and bitline BL_H: Yamada, Figure 7D) to a second voltage (To second voltage Vx”: Yamada, Figure 7D),
wherein the second voltage is higher than the first voltage (Second voltage Vx” being expressly larger than first voltage by relationship Vx” = Vinit + Vx: Yamada, Figure 7D).
Regarding Claim 16, Yamada discloses the memory device of claim 10, wherein the second charge circuit comprises:
a fourth transistor (Fourth transistor 213: Yamada, Figure 2),
wherein a first terminal and a second terminal of the fourth transistor are connected to the first sensing node and a first terminal of a fifth transistor respectively (Fourth transistor 213 connected to the sense node: Yamada, Figure 2; Note: under a broadest reasonable interpretation, ‘connected’ does not require direct connection and may include intervening circuitry); and
the fifth transistor (Fifth transistor 263 connected between the fourth transistor and the bitline: Yamada, Figure 2),
wherein a second terminal of the fifth transistor is connected to the bit line (Fifth transistor 263 connected to bit line and fourth transistor: Yamada, Figure 2), and
the control logic circuit is further configured to:
in the first charge stage and the second charge stage, apply a ramp voltage to a gate terminal of the fourth transistor until the ramp voltage rises to a fourth pass voltage (Applying a ramp voltage until passing a select pass voltage: Yamada, Figure 6); and
in the first charge stage and the second charge stage, apply a fifth pass voltage to a gate terminal of the fifth transistor to turn on the fifth transistor (Applying a pass voltage to the fifth transistor 263: Yamada, ¶[0037]).
Regarding Independent Claim 17, Yamada discloses a memory system, comprising:
at least one memory device (A memory device: Yamada, ¶[0016]),
wherein the memory device comprises:
a memory array (The memory device including a memory array: ¶[0016]); and
a page buffer circuit coupled to a bit line in the memory array (A page buffer coupled to the memory array: Yamada, ¶[0024]), wherein the page buffer circuit comprises:
a first charge circuit (First charge circuit including transistor 804: Yamada, Figure 9B),
wherein a first terminal and a second terminal of the first charge circuit are connected to a power terminal and a first sensing node respectively (The first charge circuit connecting a power terminal and a first sensing node: Yamada, Figure 9B), and
the first charge circuit is configured to:
in a first charge stage, charge the first sensing node to a first voltage (Charging to Vinit through first charge circuit including transistors 802 and 804: Yamada, Figure 9B); and
a second charge circuit (A second charge circuit including transistors 806 & 808: Yamada, Figure 10B)
coupled to the first sensing node along with the first charge circuit (The second charge circuit connected a first node along with the first charge circuit: Yamada, Figure 10B),
wherein a first terminal and a second terminal of the second charge circuit are connected to the power terminal and the bit line respectively (The second charge circuit connecting the bitline and power terminal: Yamada, Figure 10B), and the second charge circuit is configured to:
in a second charge stage (During a second charging stage: Yamada, ¶[0100]),
charge the first sensing node and the bit line (Charging the first node and bitline BL_H: Yamada, Figure 7D) to a second voltage (To second voltage Vx”: Yamada, Figure 7D),
wherein the second voltage is higher than the first voltage (Second voltage Vx” being expressly larger than first voltage by relationship Vx” = Vinit + Vx: Yamada, Figure 7D); and
a controller coupled with the at least one memory device and configured to control the memory device (A controller configure to control values of control signals: Yamada, ¶[0022).
Regarding Claim 18, Yamada discloses the memory system of claim 17, wherein the first charge circuit comprises:
a clamp transistor (Clamp transistor 804: Yamada, Figure 9B),
wherein a first terminal and a second terminal of the clamp transistor are connected to the power terminal and the first sensing node respectively (The first charge circuit 804 connected between a power terminal and the sense node: Yamada, Figure 9B), and
the memory device further comprises:
a control logic circuit (A controller configure to control values of control signals, control logic is inherent in a control logic circuit: Yamada, ¶[0022) configured to:
in the first charge stage (During the first charging stage: Yamada, ¶[0091]),
apply a third voltage to a gate terminal of the clamp transistor to turn on the clamp transistor (Applying a voltage to the clamp transistor: Yamada, ¶[0091]).
Regarding Claim 19, Yamada discloses the memory system of claim 18, wherein the second charge circuit comprises:
a first transistor (First transistor 806: Yamada, Figure 10B),
wherein a first terminal and a second terminal of the first transistor are connected to the power terminal and a second sensing node respectively (Wherein the first terminal is connected to the first sensing node and the second terminal is connected to a second node: Yamada, Figure 10B); and
a second transistor (Second transistor 808: Yamada, Figure 10B),
wherein a first terminal and a second terminal of the second transistor are connected to the second sensing node and the first sensing node respectively (Wherein the terminals of transistor 808 are connected to the second node and the power terminal: Yamada, Figure 10B), and
the control logic circuit is further configured to:
in the second charge stage (During a second charge stage: Yamada, ¶[0100]),
apply a first pass voltage to a gate terminal of the first transistor to turn on the first transistor (Applying pass voltage to the gate terminal of transistor 806: Yamada, Figure 10B), and
apply a second pass voltage to a gate terminal of the second transistor to turn on the second transistor (Applying pass voltage to the gate terminal of transistor 808: Yamada, Figure 10B).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
US 20200168276 A1 to Xiang Yang: Disclosing an overdrive circuit controlling stage pre-charging operations for a bitline
US 7453729 B2 to Yeong-Taek Lee: Disclosing a shielded bitline architecture controlling bitline charging through divided circuitry
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/CHRISTOPHER LANE REECE/Examiner, Art Unit 2824
/PHO M LUU/Primary Examiner, Art Unit 2824