DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
1. The information disclosure statements (IDS) submitted on 6/14/2024 and is in compliance with the provisions of 37 CFR 1.97. According, the information disclosure statement is being considered by the Examiner.
Examiner Notes
2. Examiner cites particular paragraphs, columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
Claim Rejections - 35 USC § 102
3. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
4. Claims 1, 5, 10, 11 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jing et al. (US. Pub. 2025/0110176; hereinafter “Jing”).
Regarding claim 1, Jing discloses a method (a method for providing a fault signal indicating detection of a fault at the test terminal, the fault condition such as a short condition, see abstract and [0016]) comprising: comparing, by a comparator (a comparator 202 in Figs. 2, 3AB and 6), an output voltage (an output voltage Vout at a test terminal SW in Fig. 1-2) of an on-chip voltage regulator (an on-die voltage regulator, see at least in [0019]) with a predefined voltage reference to detect a threshold voltage offset (“the comparator 202 compares the output voltage, Vout, with the reference voltage, Vref. In the example shown in FIG. 3A, the output voltage, Vout, is detected via the test terminal SW”, see at least in [0032]), wherein the threshold voltage offset represents an output power-ground short (“if the output voltage, Vout, is less than the reference voltage, Vref, the Prebias signal output from the first sequential logic device 302 may remain low (while the PrebiasB signal remains high), and a process is implemented to test for fault conditions associated with the test terminal SW, such as the test terminal SW being shorted to ground, the boot capacitor 114 and/or inductor 116 being missing”. See at least in [0032]); and transmitting, by an error and control logic (a fault detection logic circuitry 204, in Figs. 2-3A), a warning notification based on the threshold voltage offset (“If the test terminal SW is shorted to ground, the boot capacitor 114 will not charge, no pulse signal 402/404 will be present at the test terminal, and therefore no rising edge will be detected. Accordingly, the signal SW_rising output from the second sequential logic device 304 is low, indicating a fault”, see Fig. 4 and [0036]. “The digital logic circuit is further configured to produce, at the at least one fault detection output terminal, a fault signal based on a failure of the first test signal to transgress a threshold value within a time period, the fault signal being indicative of a fault condition at the test terminal.”, see [0066]).
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Regarding claim 5, Jing discloses the method of claim 1, further comprising for an initial chip test mode, limiting, by a current limiting circuitry of the on-chip voltage regulator, an output current of the on-chip voltage regulator; and comparing, by the comparator, the output voltage and the predefined reference voltage, to detect the output power-ground short (see paragraphs [0019, 32, 50]).
Regarding claim 10, Jing discloses the method of claim 5, further comprising applying, by the error and control logic (204), a control input to phase-locked-loop (PLL) circuits receiving the output voltage of the on-chip voltage regulator to provide a reset mode for the PLL circuits to limit a current load of the PLL circuits for the initial chip test mode (see Fig. 3A).
Regarding claim 11, Jing discloses a system (a system 100, in Fig.1, for providing a fault signal indicating detection of a fault at the test terminal, the fault condition such as a short condition, see abstract and [0016]), comprising: an on-chip voltage regulator (an on-die voltage regulator, see at least in [0019]) configured to receive a reference voltage and provide an output voltage (an output voltage Vout at a test terminal SW in Fig. 1-2); a comparator (a comparator 202 in Figs. 2, 3AB and 6) configured to compare the output voltage of the on-chip voltage regulator with a predefined reference voltage to detect a threshold voltage offset (“the comparator 202 compares the output voltage, Vout, with the reference voltage, Vref. In the example shown in FIG. 3A, the output voltage, Vout, is detected via the test terminal SW”, see at least in [0032]), wherein the threshold voltage offset represents an output power-ground short (“if the output voltage, Vout, is less than the reference voltage, Vref, the Prebias signal output from the first sequential logic device 302 may remain low (while the PrebiasB signal remains high), and a process is implemented to test for fault conditions associated with the test terminal SW, such as the test terminal SW being shorted to ground, the boot capacitor 114 and/or inductor 116 being missing”. See at least in [0032]); and an error and control logic (a fault detection logic circuitry 204, in Figs. 2-3A) configured to transmit a warning notification based on the threshold voltage offset (“If the test terminal SW is shorted to ground, the boot capacitor 114 will not charge, no pulse signal 402/404 will be present at the test terminal, and therefore no rising edge will be detected. Accordingly, the signal SW_rising output from the second sequential logic device 304 is low, indicating a fault”, see Fig. 4 and [0036]. “The digital logic circuit is further configured to produce, at the at least one fault detection output terminal, a fault signal based on a failure of the first test signal to transgress a threshold value within a time period, the fault signal being indicative of a fault condition at the test terminal.”, see [0066]).
Regarding claim 20, Jing discloses an integrated circuit (an integrated circuit 100, in Fig. 1, for providing a fault signal indicating detection of a fault at the test terminal, the fault condition such as a short condition, see abstract and [0016]), comprising: an on-chip voltage regulator (an on-die voltage regulator, see at least in [0019]) configured to receive a reference voltage and provide an output voltage (an output voltage Vout at a test terminal SW in Fig. 1-2); a comparator (a comparator 202 in Figs. 2, 3AB and 6) configured to compare the output voltage of the on-chip voltage regulator with a predefined reference voltage to detect a threshold voltage offset (“the comparator 202 compares the output voltage, Vout, with the reference voltage, Vref. In the example shown in FIG. 3A, the output voltage, Vout, is detected via the test terminal SW”, see at least in [0032]), wherein the threshold voltage offset represents an output power-ground short (“if the output voltage, Vout, is less than the reference voltage, Vref, the Prebias signal output from the first sequential logic device 302 may remain low (while the PrebiasB signal remains high), and a process is implemented to test for fault conditions associated with the test terminal SW, such as the test terminal SW being shorted to ground, the boot capacitor 114 and/or inductor 116 being missing”. See at least in [0032]); and an error and control logic (a fault detection logic circuitry 204, in Figs. 2-3A) configured to transmit a warning notification based on the threshold voltage offset (“If the test terminal SW is shorted to ground, the boot capacitor 114 will not charge, no pulse signal 402/404 will be present at the test terminal, and therefore no rising edge will be detected. Accordingly, the signal SW_rising output from the second sequential logic device 304 is low, indicating a fault”, see Fig. 4 and [0036]. “The digital logic circuit is further configured to produce, at the at least one fault detection output terminal, a fault signal based on a failure of the first test signal to transgress a threshold value within a time period, the fault signal being indicative of a fault condition at the test terminal.”, see [0066]).
5. Claims 1, 5, 11 and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Oddicini et al. (US. Pub. 2021/0143740; hereinafter “Oddicini”).
Regarding claim 1, Oddicini discloses a method (a method for determining whether an open or short fault condition is present at either the first sense terminal or the second sense terminal based on a voltage across the bridging circuit, see abstract) comprising: comparing, by a comparator (a comparator 508 in Fig. 5), an output voltage (an output voltage Vout in Fig. 1) of an on-chip voltage regulator (a voltage regulator 102 is implemented as a single unit, as a die/chip, see [0067]) with a predefined voltage reference to detect a threshold voltage offset (The comparator 508 compares a digital or analog representation of the voltage across the bridging circuit 116 to a threshold value defined by the threshold signal. The digital controller 500 determines whether a short fault (‘Short-Gnd’) is present at either voltage sense terminal VsenP(Vsen-positive), VsenN(Vsen-negative or ground) of the VR controller 100 based on a digital representation of the voltage across the bridging circuit 116. See [0037, 58]), wherein the threshold voltage offset represents an output power-ground short (“The comparator 508 generates a fault indication signal ‘osp_fault_o’ if the voltage across the bridging circuit 116 remains below the threshold value, e.g., for a certain number of measurements at the operating frequency (Fop) of the digital controller 500; see at least in [0059]. Also see [0043-44]); and transmitting, by an error and control logic (a control circuitry 108 in Fig. 1), a warning notification based on the threshold voltage offset (“If a short or open fault is present on either one of the voltage sensing lines 114, the voltage across the bridging circuit 116 in the first state will not rise above the threshold value within the defined time window. The control circuitry 108 of the VR controller 100 detects this voltage condition as a fault and may shutdown the power converter 102 and/or report the fault condition, e.g., to the load 106”, see at least in [0027]).
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Regarding claim 5, Oddicini discloses the method of claim 1, further comprising for an initial chip test mode, limiting, by a current limiting circuitry of the on-chip voltage regulator, an output current of the on-chip voltage regulator; and comparing, by the comparator, the output voltage and the predefined reference voltage, to detect the output power-ground short (see paragraphs [0052, 58-62]).
Regarding claim 11, Oddicini discloses, in Figs. 1-8, a system (a system for determining whether an open or short fault condition is present at either the first sense terminal or the second sense terminal based on a voltage across the bridging circuit, see abstract), comprising: an on-chip voltage regulator (a voltage regulator 102 is implemented as a single unit, as a die/chip, see [0067]) configured to receive a reference voltage and provide an output voltage (an output voltage Vout in Fig. 1); a comparator (a comparator 508 in Fig. 5) configured to compare the output voltage of the on-chip voltage regulator with a predefined reference voltage to detect a threshold voltage offset (The comparator 508 compares a digital or analog representation of the voltage across the bridging circuit 116 to a threshold value defined by the threshold signal. The digital controller 500 determines whether a short fault (‘Short-Gnd’) is present at either voltage sense terminal VsenP(Vsen-positive), VsenN(Vsen-negative or ground) of the VR controller 100 based on a digital representation of the voltage across the bridging circuit 116. See [0037, 58]), wherein the threshold voltage offset represents an output power-ground short (“The comparator 508 generates a fault indication signal ‘osp_fault_o’ if the voltage across the bridging circuit 116 remains below the threshold value, e.g., for a certain number of measurements at the operating frequency (Fop) of the digital controller 500; see at least in [0059]. Also see [0043-44]); and an error and control logic (a control circuitry 108 in Fig. 1) configured to transmit a warning notification based on the threshold voltage offset (“If a short or open fault is present on either one of the voltage sensing lines 114, the voltage across the bridging circuit 116 in the first state will not rise above the threshold value within the defined time window. The control circuitry 108 of the VR controller 100 detects this voltage condition as a fault and may shutdown the power converter 102 and/or report the fault condition, e.g., to the load 106”, see at least in [0027]).
Regarding claim 20, Oddicini discloses an integrated circuit (a controller circuit for determining whether an open or short fault condition is present at either the first sense terminal or the second sense terminal based on a voltage across the bridging circuit, see Fig. 1 and abstract), comprising: an on-chip voltage regulator (a voltage regulator 102 is implemented as a single unit, as a die/chip, see [0067]) configured to receive a reference voltage and provide an output voltage (an output voltage Vout in Fig. 1); a comparator (a comparator 508 in Fig. 5) configured to compare the output voltage of the on-chip voltage regulator with a predefined reference voltage to detect a threshold voltage offset (The comparator 508 compares a digital or analog representation of the voltage across the bridging circuit 116 to a threshold value defined by the threshold signal. The digital controller 500 determines whether a short fault (‘Short-Gnd’) is present at either voltage sense terminal VsenP(Vsen-positive), VsenN(Vsen-negative or ground) of the VR controller 100 based on a digital representation of the voltage across the bridging circuit 116. See [0037, 58]), wherein the threshold voltage offset represents an output power-ground short (“The comparator 508 generates a fault indication signal ‘osp_fault_o’ if the voltage across the bridging circuit 116 remains below the threshold value, e.g., for a certain number of measurements at the operating frequency (Fop) of the digital controller 500; see at least in [0059]. Also see [0043-44]); and an error and control logic (a control circuitry 108 in Fig. 1) configured to transmit a warning notification based on the threshold voltage offset (“If a short or open fault is present on either one of the voltage sensing lines 114, the voltage across the bridging circuit 116 in the first state will not rise above the threshold value within the defined time window. The control circuitry 108 of the VR controller 100 detects this voltage condition as a fault and may shutdown the power converter 102 and/or report the fault condition, e.g., to the load 106”, see at least in [0027]).
Claim Rejections - 35 USC § 103
6. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
7. Claims 6-8 and 15-17 are rejected under 35 U.S.C. 103 as being unpatentable over Jing in view of Takano et al. (US. Pub. 2017/0063232; hereinafter “Takano”).
Regarding claim 6, Jing discloses the method of claim 5, except for specifying that the on-chip voltage regulator comprises a plurality of output current tiles supplying the output current, further comprising the current limiting circuitry selectively enabling at least one of the plurality of output current tiles, and disabling other ones of the plurality of output current tiles, to limit the output current of the on-chip voltage regulator for the initial chip test mode. Takano discloses, in Fig. 1, a semiconductor integrated circuit device (10) for voltage regulator comprising a plurality of output current tiles (Q1-Q4) supplying the output current (X1, Xn), further comprising the current limiting circuitry selectively enabling at least one of the plurality of output current tiles (transistors Q1-Q4 are configured to function as witches for enabling one of output current tiles X1-Xn), and disabling other ones of the plurality of output current tiles (transistors Q1-Q4 are configured to function as witches for disabling one of output current tiles X1-Xn), to limit the output current of the on-chip voltage regulator for the initial chip test mode (see Fig. 1).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the fault detection system of Jing by having a plurality of output current tiles supplying the output current, further comprising the current limiting circuitry selectively enabling at least one of the plurality of output current tiles, and disabling other ones of the plurality of output current tiles, to limit the output current of the on-chip voltage regulator for the initial chip test mode, as taught by Takano for purpose of providing the circuit so that reduces burden of a controlling apparatus controlling a system when the open-circuit and the short-circuit of the load is determined and a detecting signal is output externally in the semiconductor integrated circuit for the regulator.
Regarding claim 7, Jing and Takano disclose the method of claim 6, Takano further teaches wherein the current limiting circuitry comprises a plurality of enable transistors (Q1-Q4), with a respective enable transistor connected in series with an associated output current tile (Fig. 1 shows that a plurality of enable transistors Q1-Q4 with a respective enable transistor connected in series with an associated output current tile X1, Xn, see Fig. 1), and the enable transistors receiving a gate control signal (an output control signal of an error amplifier 11 coupled to a control gate of Q1-Q4) to turn on the enable transistors for selectively enabling at least one of the plurality of output current tiles (see Fig. 1 and [0029-30]).
Regarding claim 8, Jing discloses the method of claim 5, except for specifying that the on-chip voltage regulator comprises a plurality of output current tiles supplying the output current, and the current limiting circuitry selectively provides a reference current to the plurality of output current tiles to limit the output current of the on-chip voltage regulator for the initial chip test mode.
Takano discloses, in Fig. 1, a semiconductor integrated circuit device (10) for voltage regulator comprising comprises a plurality of output current tiles (a plurality of output current tiles X1, Xn, see Fig. 1) supplying the output current, and the current limiting circuitry selectively provides a reference current to the plurality of output current tiles to limit the output current of the on-chip voltage regulator for the initial chip test mode (transistors Q1-Q4 are configured for selectively providing a reference current to the plurality of output current tiles to limit the output current of the on-chip voltage regulator during the detection mode. See Fig. 1 and [0029-30]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the fault detection system of Jing by a plurality of output current tiles supplying the output current, and the current limiting circuitry selectively provides a reference current to the plurality of output current tiles to limit the output current of the on-chip voltage regulator for the initial chip test mode, as taught by Takano for purpose of providing the circuit so that reduces burden of a controlling apparatus controlling a system when the open-circuit and the short-circuit of the load is determined and a detecting signal is output externally in the semiconductor integrated circuit for the regulator.
Regarding claim 15, Jing discloses the system of claim 11, except for explicitly specifying wherein the on-chip voltage regulator comprises a plurality of output current tiles supplying an output current of the on-chip voltage regulator, and a current limiting circuitry configured to limit the output current of the on-chip voltage regulator for an initial chip test mode.
Takano discloses, in Fig. 1, a semiconductor integrated circuit device (10) for voltage regulator comprising a plurality of output current tiles (Q1-Q4) supplying an output current of the on-chip voltage regulator, and a current limiting circuitry configured to limit the output current of the on-chip voltage regulator for an initial chip test mode (transistors Q1-Q4 are configured for selectively providing a reference current to the plurality of output current tiles to limit the output current of the on-chip voltage regulator during the detection mode. See Fig. 1 and [0029-30]).
It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to employ the fault detection system of Jing by having a plurality of output current tiles supplying an output current of the on-chip voltage regulator, and a current limiting circuitry configured to limit the output current of the on-chip voltage regulator for an initial chip test mode, as taught by Takano for purpose of providing the circuit so that reduces burden of a controlling apparatus controlling a system when the open-circuit and the short-circuit of the load is determined and a detecting signal is output externally in the semiconductor integrated circuit for the regulator.
Regarding claim 16, Jing and Takano disclose the system of claim 15, Takano further teaches wherein the current limiting circuitry comprises a plurality of enable transistors (Q1-Q4), wherein the enable transistors (Q1-Q4) are connected in series with associated output current tiles (see Fig. 1), and the enable transistors are configured to receive a control gate input to selectively enable an associated output current tile to supply output current for the initial chip test mode (see Fig. 1 and [0029-30]).
Regarding claim 17, Jing and Takano disclose the system of claim 15, Takano further teaches wherein the current limiting circuitry is configured to apply a reference current to the plurality of output current tiles to limit the output current supplied by the plurality of output current tiles for the initial chip test mode (see Fig. 1 and [0029-30]).
Allowable Subject Matter
8. Claims 2-4, 9, 12-14, 18-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
9. The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 2, the cited references, alone or in combination, do not disclose nor fairly suggest:
“ …comparing, by a series of comparators that includes the comparator, the output voltage with a plurality of predefined voltage references; and detecting respective threshold voltage offsets by the series of comparators to monitor degraded values of the output power-ground short.” in combination with all other elements as claimed in claim 1.
As to claim(s) 3-4, the claims are allowable as they are further limitation of claim 2.
Regarding claim 9, the cited references, alone or in combination, do not disclose nor fairly suggest:
“ … the current limiting circuitry comprises a current source coupled to a catch diode, a reference transistor coupled to the catch diode to provide the reference current to the plurality of output current tiles based on the current source, and a current limiting transistor selectively coupled to the catch diode by a throttle select switch to limit the reference current provided to the plurality of output current tiles for the initial chip test mode.” in combination with all other elements as claimed in claims 1, 5 and 8.
Regarding claim 12, the cited references, alone or in combination, do not disclose nor fairly suggest:
“ … a series of comparators configured to compare the output voltage with a plurality of predefined voltage references, and detect respective threshold voltage offsets by the series of comparators, to monitor degraded values of the output power-ground short; and wherein the error and control logic is configured to transmit a series of warning notifications, based on the degraded values of the output power-ground short” in combination with all other elements as claimed in claim 11.
As to claim(s) 13-14, the claims are allowable as they are further limitation of claim 12.
Regarding claim 18, the cited references, alone or in combination, do not disclose nor fairly suggest:
“ … the current limiting circuitry comprises a current source coupled to a catch diode, a reference transistor coupled to the catch diode to provide the reference current to the plurality of output current tiles based on the current source; and a current limiting transistor selectively coupled to the catch diode by a throttle select switch, to limit the reference current provided by the reference transistor for the initial chip test mode.” in combination with all other elements as claimed in claims 11, 15 and 17.
As to claim(s) 19, the claim is allowable as it is further limitation of claim 18.
Prior Art of Record
10. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Colarossi (U.S Pub. 2021/0344189) discloses a voltage regulator (see specification for more details).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THANG LE whose telephone number is (571)272-9349. The examiner can normally be reached on Monday thru Friday 7:30AM-5:00PM EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Huy Phan can be reached on (571) 272-7924. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/THANG X LE/Primary Examiner, Art Unit 2858
4/24/2026
Prosecution Insights