DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/14/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner and made of record.
Claim Objections
Claim 6 is objected to because of the following informalities: Claim 6 is missing the period after the number 6.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(B) CONCLUSION. - The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 4, 17 and 22 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 4, recite “the second side surface of the second part” and “the second side surface of the first part”. There is insufficient antecedent basis for these limitations in the claims. Claim 4 is dependent on claim 3 and further dependent on claim 2 and 1. However, claims 1-3 do not recite “a second side surface of the second part” and “a second side surface of the first part”. Therefore, it is unclear, and the scope of the claims are unclear.
Claim 17, recite “the light emitting element”. There is insufficient antecedent basis for these limitations in the claims. Claim 17 is dependent on claim 16 and further dependent on claim 15. However, claims 15-16 do not recite “a light emitting element”. Claim 15 recited a plurality of light emitting elements. Therefore, it is unclear, and the scope of the claims are unclear.
Claim 22, recite “the first width of the first part and the second width of the second part.”. There is insufficient antecedent basis for these limitations in the claims. Claim 22 is dependent on claim 18. However, claim 18 does not recite “a first width of the first part and a second width of the second part.”. Therefore, it is unclear, and the scope of the claims are unclear.
Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2-7, 9, 13-14 are rejected under 35 U.S.C. 103 as being unpatentable over SUNG; Youn Joon (US 20190013439 A1) “SUNG et al.” in view of Check; Michael (US 20230037469 A1) “Check et al.”.
Regarding Independent Claim 1, SUNG et al. Figs. 1-8 discloses a light emitting element (“a semiconductor device 100” ¶ [0034]), comprising:
a first semiconductor layer (“a first conductive-type semiconductor layer 122” ¶ [0037]);
a first electrode (“a first electrode 132” ¶ [0035]), and
an active layer (“an active layer 124” ¶ [0037]) disposed on the first semiconductor layer 122; the first electrode 132 being spaced apart (Fig. 2 shows the first electrode 132 being spaced apart from the active layer 124) from the active layer 124;
a second semiconductor layer (“a second conductive-type semiconductor layer 126” ¶ [0037]) disposed on the active layer 124; and
a second electrode (“a second electrode 134” ¶ [0035]) disposed on the second semiconductor layer 126,
However, SUNG et al. does not disclose, the active layer includes:
a plurality of first parts having a first width in a width direction; and
a second part disposed between at least two of the plurality of first parts, the second part having a second width smaller than the first width in the width direction.
In the similar field of endeavor of LED devices, Check et al. Figs. 1-2, 3A-3B, 4 and 7B discloses wherein the active layer 18 (“an active layer 18” ¶ [0044]) includes:
a plurality of first parts (“each individual feature 58 abuts at least one neighboring feature 58 at an intersection 60 therebetween. Each intersection of 60 may be formed by intersecting surfaces of next-adjacent features 58. For example, next-adjacent features 58-1, 58-2 form an intersection 60-1 along one of the mesa sidewalls 50′.” ¶ [0053]; “mesa 50 may include the p-type layer 14, the active layer 18, and a portion of the n-type layer 16.” ¶ [0048]) having a first width in a width direction (“an arrangement, the intersections 60 form sharp protrusions of the mesa sidewall 50′ for redirecting light” ¶ [0063]); and
a second part (Fig. 7B shows inwardly curved 58 in 50) disposed between at least two of the plurality of first parts (“Each intersection of 60 may be formed by intersecting surfaces of next-adjacent features 58. For example, next-adjacent features 58-1, 58-2 form an intersection 60-1 along one of the mesa sidewalls 50′.” ¶ [0053]), the second part having a second width smaller than the first width in the width direction (Fig. 7B and 8A show dimension alternates between larger at the protrusions and smaller at the intersections).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the active layer of SUNG et al. with the active layer of Check et al. in order to redirect light in desired emission directions while reducing amounts of light that exit mesa sidewalls. Patterns may be continuous along all mesa sidewalls and corresponding corners, or the patterns may be discontinuous along one or more portions of mesa sidewalls depending on desired emission profiles for corresponding LED chips (Check et al. ¶ [0060]).
Regarding Claim 2, SUNG et al. as modified by Check et al. discloses the limitations of claim 1. However, SUNG et al. does not disclose, wherein the first semiconductor layer, the active layer, and the second semiconductor layer have rounded corners,
wherein the first semiconductor layer has a constant width in the width direction except for the rounded corners of the first semiconductor layer.
In the similar field of endeavor of LED devices, Check et al. Fig. 3A further discloses, wherein the first semiconductor layer, the active layer, and the second semiconductor layer have rounded corners (“forms a mesa 50 with a mesa sidewall 50′. The mesa 50 may include the p-type layer 14, the active layer 18, and a portion of the n-type layer 16.” ¶ [0048]; Fig. 3 shows the rounded corner),
wherein the first semiconductor layer 16 has a constant width in the width direction except for the rounded corners of the first semiconductor layer 16 (Figs. 1-2 show the 16 has a constant width in the width direction except for the rounded corners of the first semiconductor layer 16).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the active layer of SUNG et al. with the active layer of Check et al. in order to redirect light in desired emission directions while reducing amounts of light that exit mesa sidewalls. Patterns may be continuous along all mesa sidewalls and corresponding corners, or the patterns may be discontinuous along one or more portions of mesa sidewalls depending on desired emission profiles for corresponding LED chips (Check et al. ¶ [0060]).
Regarding Claim 3, SUNG et al. as modified by Check et al. discloses the limitations of claim 2. SUNG et al. Figs. 1-8 and 11 further discloses, further comprising:
a first plane on the first semiconductor layer (“a region (hereinafter referred to as a first region S1) of the first conductive-type semiconductor layer 122 in which the first electrode 132 is disposed.” ¶ [0050]), the first electrode being disposed on the first plane of the first semiconductor layer 122;
first side surfaces (“the side surface of the light emitting structure 120 is inclined with respect to the upper surface of the substrate 110, one end thereof is in contact with the substrate 110” ¶ [0100]) extending in a downward direction from the first plane (“the side surface of the light emitting structure 120 is inclined with respect to the upper surface of the substrate 110, one end thereof is in contact with the substrate 110” ¶ [0100]); and
second side surfaces (“inclined side surface 120a” ¶ [0054]) extending in an upward direction from the first plane (“An inclined side surface 120a is disposed between the upper surface 126a of the second conductive-type semiconductor layer 126 and the first region S1 of the first conductive-type semiconductor layer 122.” ¶ [0054]), wherein a distance between the first side surfaces facing each other in the width direction is constant (“semiconductor device package 835 may be the above-described embodiment.” ¶ [0153]; Fig. 11 shows 835 is rectangular shape, the peripheral outline being a rectangle, therefore, distance between the first side surfaces facing each other in the width direction is constant),
However, SUNG et al. does not disclose, wherein a distance between the second side surfaces facing each other in the width direction in the plurality of first parts is longer than a distance between the second side surfaces facing in the width direction in the second part.
In the similar field of endeavor of LED devices, Check et al. Figs. 1-2, 3A-3B, 4 and 7B discloses wherein a distance between the second side surfaces facing each other in the width direction in the plurality of first parts is longer than a distance between the second side surfaces facing in the width direction in the second part (“Each intersection of 60 may be formed by intersecting surfaces of next-adjacent features 58. For example, next-adjacent features 58-1, 58-2 form an intersection 60-1 along one of the mesa sidewalls 50′.” ¶ [0053]; Fig. 7B and 8A show dimension alternates between larger at the protrusions and smaller at the intersections).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the active layer of SUNG et al. with the active layer of Check et al. in order to redirect light in desired emission directions while reducing amounts of light that exit mesa sidewalls. Patterns may be continuous along all mesa sidewalls and corresponding corners, or the patterns may be discontinuous along one or more portions of mesa sidewalls depending on desired emission profiles for corresponding LED chips (Check et al. ¶ [0060]).
Regarding Claim 4, SUNG et al. as modified by Check et al. discloses the limitations of claim 3. However, SUNG et al. does not disclose, wherein at least a portion of the second side surface of the second part is disposed inside the second side surface of the first part.
In the similar field of endeavor of LED devices, Check et al. Figs. 1-2, 3A-3B, 4 and 7B discloses wherein at least a portion of the second side surface of the second part is disposed inside the second side surface of the first part (“Each intersection of 60 may be formed by intersecting surfaces of next-adjacent features 58. For example, next-adjacent features 58-1, 58-2 form an intersection 60-1 along one of the mesa sidewalls 50′.” ¶ [0053]; Fig. 7B and 8A show dimension alternates between larger at the protrusions and smaller at the intersections).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the active layer of SUNG et al. with the active layer of Check et al. in order to redirect light in desired emission directions while reducing amounts of light that exit mesa sidewalls. Patterns may be continuous along all mesa sidewalls and corresponding corners, or the patterns may be discontinuous along one or more portions of mesa sidewalls depending on desired emission profiles for corresponding LED chips (Check et al. ¶ [0060]).
Regarding Claim 5, SUNG et al. as modified by Check et al. discloses the limitations of claim 3. However, SUNG et al. does not disclose, wherein a shortest distance between the first side surface and the second side surface on one side of the light emitting element is equal to or substantially equal to a shortest distance between the first side surface and the second side surface on another side of the light emitting element in the width direction.
In the similar field of endeavor of LED devices, Check et al. Figs. 1-2, 3A-3B, 4 and 7B discloses wherein a shortest distance between the first side surface and the second side surface on one side of the light emitting element is equal to or substantially equal to a shortest distance between the first side surface and the second side surface on another side of the light emitting element in the width direction (“FIG. 4 is a bottom view of an exemplary LED chip 64 that includes a repeating pattern of features 58 along mesa sidewalls 50′” ¶ [0056]; Fig. 4 show wherein a shortest distance between the first side surface and the second side surface on one side of the light emitting element is equal to or substantially equal to a shortest distance between the first side surface and the second side surface on another side of the light emitting element in the width direction).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the distances between the side surfaces of SUNG et al. with the distances between the side surfaces of Check et al. in order to providing more light-emitting area within the active LED structure mesa and a brighter overall light output for the LED chip (Check et al. ¶ [0058]).
Regarding Claim 6, SUNG et al. as modified by Check et al. discloses the limitations of claim 3. SUNG et al. further discloses, wherein a shortest distance between the first side surface and the second side surface on one side of the light emitting element is smaller than a shortest distance between the first side surface and the second side surface on another side of the light emitting element in the width direction (“For alignment margin for patterning, the distance d4 between the second edge 301b of the inclined side surface 120a and the first electrode 132 may be at least 10 μm, and the distance d3 between the first edge 301a of the inclined side surface 120a and the second electrode 134 may be at least 10 μm.” ¶ [0090]; the region S1 required to land 132 with 10 μm alignment margin exists in one side only, therefore, the other side is without any alignment margin is smaller).
Regarding Claim 7, SUNG et al. as modified by Check et al. discloses the limitations of claim 6. SUNG et al. Figs. 7A-7B and 8A-8E further discloses, wherein an inclination angle (“the angle θ2 between the inclined side surface 120a and the upper surface of the first region S1 at the second edge 301b may be 115° to 120°” ¶ [0078]) of the second side surface of at least one of the plurality of first parts on the one side is larger than an inclination angle (“the internal angle θ of the inclined side surface 120a may be 41° to 65°.” ¶ [0074]) of the second side surface of the at least one of the plurality of first parts on the another side.
Regarding Claim 9, SUNG et al. as modified by Check et al. discloses the limitations of claim 6. However, SUNG et al. does not disclose, wherein the second part is one of a plurality of second parts, and wherein the plurality of first parts and the plurality of second parts are alternately disposed.
In the similar field of endeavor of LED devices, Check et al. Figs. 1-2, 3A-3B, 4, 7A-7B and 8A-8E discloses, wherein the second part is one of a plurality of second parts, and wherein the plurality of first parts and the plurality of second parts are alternately disposed (“Each intersection of 60 may be formed by intersecting surfaces of next-adjacent features 58. For example, next-adjacent features 58-1, 58-2 form an intersection 60-1 along one of the mesa sidewalls 50′.” ¶ [0053]; Fig. 7B and 8 show dimension alternates between larger at the protrusions and smaller at the intersections).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the active layer of SUNG et al. with the active layer of Check et al. in order to redirect light in desired emission directions while reducing amounts of light that exit mesa sidewalls. Patterns may be continuous along all mesa sidewalls and corresponding corners, or the patterns may be discontinuous along one or more portions of mesa sidewalls depending on desired emission profiles for corresponding LED chips (Check et al. ¶ [0060]).
Regarding Claim 13, SUNG et al. as modified by Check et al. discloses the limitations of claim 6. However, SUNG et al. does not disclose, wherein the second width increases as a distance away from a center of the second part increases.
In the similar field of endeavor of LED devices, Check et al. Figs. 1-2, 3A-3B, 4, 7A-7B and 8A-8E discloses, wherein the second width increases as a distance away from a center of the second part increases (“Each intersection of 60 may be formed by intersecting surfaces of next-adjacent features 58. For example, next-adjacent features 58-1, 58-2 form an intersection 60-1 along one of the mesa sidewalls 50′.” ¶ [0053]; Fig. 7B and 8 show dimension alternates between larger at the protrusions and smaller at the intersections).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the active layer of SUNG et al. with the active layer of Check et al. in order to redirect light in desired emission directions while reducing amounts of light that exit mesa sidewalls. Patterns may be continuous along all mesa sidewalls and corresponding corners, or the patterns may be discontinuous along one or more portions of mesa sidewalls depending on desired emission profiles for corresponding LED chips (Check et al. ¶ [0060]).
Regarding Claim 14, SUNG et al. as modified by Check et al. discloses the limitations of claim 1. SUNG et al. Figs. 1-2 and 4 further discloses, further comprising:
an encapsulation film (“a passivation layer 140” ¶ [0035]) covering a top surface and a side surface of the light emitting element (Figs 2 and 4 shows 140 covers a top surface and a side surface of the light emitting element 120),
wherein the encapsulation film covers all side surfaces of the second semiconductor layer and all side surfaces of the active layer, and covers a portion of a side surface of the first semiconductor layer (“the passivation layer 140 may cover the side surface of the first conductive-type semiconductor layer 122, the side surface of the active layer 124, the side surface of the second conductive-type semiconductor layer 126, and the inclined side surface 120a. In addition, the passivation layer 140 may cover a portion of the upper surface of the second conductive-type semiconductor layer 126 except for a region in which the second electrode 134 is disposed.” ¶ [0098]).
Claims 15-21 are rejected under 35 U.S.C. 103 as being unpatentable over LEE; Sang Youl (US 20210036187 A1) “LEE et al.” in view of Check; Michael (US 20230037469 A1) “Check et al.”.
Regarding Independent Claim 15, LEE et al. Figs. 1-13 discloses a display device (“a semiconductor device” ¶ [0042]; “a display apparatus to which a semiconductor device is transferred according to an embodiment.” ¶ [0241]), comprising:
a plurality of light emitting elements disposed on a substrate (“a semiconductor device including a plurality of semiconductor devices disposed on a substrate 110” ¶ [0173]),
wherein each of the plurality of light emitting elements includes:
a first semiconductor layer (“a first conductive semiconductor layer 12” ¶ [0042]);
a first electrode (“a first electrode 15 electrically connected to the first semiconductor layer 12” ¶ [0042]) and
an active layer (“an active layer 13 disposed between the first conductive semiconductor layer 12 and the second conductive semiconductor layer 14,” ¶ [0042]) disposed on the first semiconductor layer 12;
a second semiconductor layer (“a second conductive semiconductor layer 14” ¶ [0042]) on the active layer 13; and
a second electrode (“a second electrode 16 electrically connected to the second semiconductor layer 14” ¶ [0042]) disposed on the second semiconductor layer 14, the second electrode 16 being apart from the first electrode 15.
However, SUNG et al. does not disclose, wherein the active layer includes:
a first part having a first width; and
a second part having a same width as a width of the first part in longitudinal direction and having a second width smaller than the first width in a width direction.
In the similar field of endeavor of LED devices, Check et al. Figs. 1-2, 3A-3B, 4 and 7B discloses wherein the active layer 18 (“an active layer 18” ¶ [0044]) includes:
a first part (“each individual feature 58 abuts at least one neighboring feature 58 at an intersection 60 therebetween. Each intersection of 60 may be formed by intersecting surfaces of next-adjacent features 58. For example, next-adjacent features 58-1, 58-2 form an intersection 60-1 along one of the mesa sidewalls 50′.” ¶ [0053]; “mesa 50 may include the p-type layer 14, the active layer 18, and a portion of the n-type layer 16.” ¶ [0048]) having a first width (“an arrangement, the intersections 60 form sharp protrusions of the mesa sidewall 50′ for redirecting light” ¶ [0063]); and
a second part (Fig. 7B shows inwardly curved 58 in 50) having a same width as a width of the first part in longitudinal direction and (“Each intersection of 60 may be formed by intersecting surfaces of next-adjacent features 58. For example, next-adjacent features 58-1, 58-2 form an intersection 60-1 along one of the mesa sidewalls 50′.” ¶ [0053]), having a second width smaller than the first width in a width direction (Fig. 7B and 8A show dimension alternates between larger at the protrusions and smaller at the intersections).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the active layer of SUNG et al. with the active layer of Check et al. in order to redirect light in desired emission directions while reducing amounts of light that exit mesa sidewalls. Patterns may be continuous along all mesa sidewalls and corresponding corners, or the patterns may be discontinuous along one or more portions of mesa sidewalls depending on desired emission profiles for corresponding LED chips (Check et al. ¶ [0060]).
Regarding Claim 16, LEE et al. as modified by Check et al. discloses the limitations of claim 15. LEE et al. further discloses, wherein each of the plurality of light emitting elements further includes:
a first side surface disposed below the first electrode; and a second side surface disposed above the first electrode, the second side surface being spaced apart from the first side surface (“side surfaces S2, S3, S4, and S5 of the semiconductor structure 140 and may include a first hole H1 through which the first electrode 15 is to be exposed” ¶ [0044]),
wherein the second side surface of the first part includes at least one surface having different inclination angles (“A first angle θ2 between the inclined surface S12 and a virtual horizontal surface may range from 20° to 80° or from 20° to 50°.” ¶ [0051]; (“a second angle θ.sub.1 between the horizontal surface and the side surfaces S2, S3, S4, and S5 of the semiconductor structure 140 may range from 70° to 90°.” ¶ [0052]), and wherein the second side surface of the second part has a same inclination angle (“a second angle θ.sub.1 between the horizontal surface and the side surfaces S2, S3, S4, and S5 of the semiconductor structure 140 may range from 70° to 90°.” ¶ [0052]).
Regarding Claim 17, LEE et al. as modified by Check et al. discloses the limitations of claim 16. LEE et al. further discloses, wherein the active layer is disposed closer to a first side of the light emitting element than a second side of the light emitting element that is opposite to the first side (“The area of the first upper surface S11 may range from 30% to 110% of the area of the second upper surface S13. As an example, the area of the first upper surface S11 may range from 40% to 110% of the area of the second upper surface S13.” ¶ [0046]).
Regarding Independent Claim 18, LEE et al. Figs. 1-13 discloses a light emitting element comprising:
a first semiconductor layer (“a first conductive semiconductor layer 12” ¶ [0042]);
a first electrode (“a first electrode 15 electrically connected to the first semiconductor layer 12” ¶ [0042]) disposed on the first semiconductor layer;
an active layer (“an active layer 13 disposed between the first conductive semiconductor layer 12 and the second conductive semiconductor layer 14,” ¶ [0042]) disposed on the first semiconductor layer 12;
the active layer 13 being spaced apart (Fig. 1 shows 13 is spaced apart from 15) from the first electrode 15;
a second semiconductor layer (“a second conductive semiconductor layer 14” ¶ [0042]) disposed on the active layer 13; and
a second electrode (“a second electrode 16 electrically connected to the second semiconductor layer 14” ¶ [0042]) disposed on the second semiconductor layer 14,
the second electrode 16 being apart from the first electrode 15.
However, SUNG et al. does not disclose, wherein a first part of the active layer between the first electrode and the second electrode is wider than a second part of the active layer between the first electrode and the second electrode.
In the similar field of endeavor of LED devices, Check et al. Figs. 1-2, 3A-3B, 4 and 7B discloses wherein the active layer 18 (“an active layer 18” ¶ [0044]) includes:
a first part (“each individual feature 58 abuts at least one neighboring feature 58 at an intersection 60 therebetween. Each intersection of 60 may be formed by intersecting surfaces of next-adjacent features 58. For example, next-adjacent features 58-1, 58-2 form an intersection 60-1 along one of the mesa sidewalls 50′.” ¶ [0053]; “mesa 50 may include the p-type layer 14, the active layer 18, and a portion of the n-type layer 16.” ¶ [0048]) a first part of the active layer between the first electrode and the second electrode is wider than (“an arrangement, the intersections 60 form sharp protrusions of the mesa sidewall 50′ for redirecting light” ¶ [0063]) a second part (Fig. 7B shows inwardly curved 58 in 50) of the active layer between the first electrode and the second electrode (“Each intersection of 60 may be formed by intersecting surfaces of next-adjacent features 58. For example, next-adjacent features 58-1, 58-2 form an intersection 60-1 along one of the mesa sidewalls 50′.” ¶ [0053]), having a second width smaller than the first width in a width direction (Fig. 7B and 8A show dimension alternates between larger at the protrusions and smaller at the intersections).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the active layer of SUNG et al. with the active layer of Check et al. in order to redirect light in desired emission directions while reducing amounts of light that exit mesa sidewalls. Patterns may be continuous along all mesa sidewalls and corresponding corners, or the patterns may be discontinuous along one or more portions of mesa sidewalls depending on desired emission profiles for corresponding LED chips (Check et al. ¶ [0060]).
Regarding Claim 19, LEE et al. as modified by Check et al. discloses the limitations of claim 18. However, LEE et al. does not disclose wherein a width of the active layer varies in a region between the first electrode and the second electrode.
In the similar field of endeavor of LED devices, Check et al. Figs. 1-2, 3A-3B, 4 and 7B discloses wherein a width of the active layer 18 (“an active layer 18” ¶ [0044]) varies in a region between the first electrode and the second electrode (“each individual feature 58 abuts at least one neighboring feature 58 at an intersection 60 therebetween. Each intersection of 60 may be formed by intersecting surfaces of next-adjacent features 58. For example, next-adjacent features 58-1, 58-2 form an intersection 60-1 along one of the mesa sidewalls 50′.” ¶ [0053]; “mesa 50 may include the p-type layer 14, the active layer 18, and a portion of the n-type layer 16.” ¶ [0048]; “an arrangement, the intersections 60 form sharp protrusions of the mesa sidewall 50′ for redirecting light” ¶ [0063]; Fig. 7B shows inwardly curved 58 in 50; “Each intersection of 60 may be formed by intersecting surfaces of next-adjacent features 58. For example, next-adjacent features 58-1, 58-2 form an intersection 60-1 along one of the mesa sidewalls 50′.” ¶ [0053]; Fig. 7B and 8A show dimension alternates between larger at the protrusions and smaller at the intersections).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify the active layer of LEE et al. with the active layer of Check et al. in order to redirect light in desired emission directions while reducing amounts of light that exit mesa sidewalls. Patterns may be continuous along all mesa sidewalls and corresponding corners, or the patterns may be discontinuous along one or more portions of mesa sidewalls depending on desired emission profiles for corresponding LED chips (Check et al. ¶ [0060]).
Regarding Claim 20, LEE et al. as modified by Check et al. discloses the limitations of claim 18. LEE et al. further discloses wherein the second semiconductor layer 14, the active layer 13 and a portion (“a second sub-semiconductor layer 12b which is disposed between the first sub-semiconductor layer 12a and the active layer 13” ¶ [0055]) of the first semiconductor layer 12 form a stacked structure (Fig. 1 shows 14, 13 and 12b have a stacked mesa shape ) having a mesa shape (“first sub-semiconductor layer 12a may be exposed by mesa-etching” ¶ [0060]), and
wherein the opposite sides of the mesa shape have different angles of inclination (“A first angle θ2 between the inclined surface S12 and a virtual horizontal surface may range from 20° to 80° or from 20° to 50°.” ¶ [0051]; “a second angle θ.sub.1 between the horizontal surface and the side surfaces S2, S3, S4, and S5 of the semiconductor structure 140 may range from 70° to 90°.” ¶ [0052]).
Regarding Claim 21, LEE et al. as modified by Check et al. discloses the limitations of claim 20. LEE et al. further discloses wherein the mesa shape is disposed closer to a first side of the light emitting element than a second side of the light emitting element (“The area of the first upper surface S11 may range from 30% to 110% of the area of the second upper surface S13. As an example, the area of the first upper surface S11 may range from 40% to 110% of the area of the second upper surface S13.” ¶ [0046]).
Claims 1-2 are rejected under 35 U.S.C. 103 as being unpatentable over Check; Michael (US 20230037469 A1) “Check et al.”. in view of HARUTA; Yuki (US 20140103391 A1) “HARUTA et al.”
Regarding Independent Claim 1, Check et al. Figs. 1-2, 3A-3B, 4 and 7B discloses a light emitting element (“an LED chip 10” ¶ [0044]), comprising:
a first semiconductor layer (“an n-type layer 16” ¶ [0044]);
a first electrode (“an n-contact 40” ¶ [0047]) and
an active layer (“an active layer 18” ¶ [0044]) disposed on the first semiconductor layer 16 (Figs. 1-2 shows 18 disposes on 16); the first electrode 40 being spaced apart (Figs. 1-2 shows 40 is spaced apart from 18) from the active layer 18;
a second semiconductor layer (“a p-type layer 14” ¶ [0044]) disposed on the active layer 18 (Fig. 2 shows 14 disposed on 18); and
a second electrode (“a p-contact 38” ¶ [0047]) disposed on the second semiconductor layer 14,
wherein the active layer 18 includes:
a plurality of first parts (“each individual feature 58 abuts at least one neighboring feature 58 at an intersection 60 therebetween. Each intersection of 60 may be formed by intersecting surfaces of next-adjacent features 58. For example, next-adjacent features 58-1, 58-2 form an intersection 60-1 along one of the mesa sidewalls 50′.” ¶ [0053]; “mesa 50 may include the p-type layer 14, the active layer 18, and a portion of the n-type layer 16.” ¶ [0048]) having a first width in a width direction (“an arrangement, the intersections 60 form sharp protrusions of the mesa sidewall 50′ for redirecting light” ¶ [0063]); and
a second part (Fig. 7B shows inwardly curved 58 in 50) disposed between at least two of the plurality of first parts (“Each intersection of 60 may be formed by intersecting surfaces of next-adjacent features 58. For example, next-adjacent features 58-1, 58-2 form an intersection 60-1 along one of the mesa sidewalls 50′.” ¶ [0053]), the second part having a second width smaller than the first width in the width direction (Fig. 7B and 8A show dimension alternates between larger at the protrusions and smaller at the intersections).
However, Check et al. does not explicitly show the first electrode being spaced apart from the active layer.
In the similar field of endeavor of LED devices, HARUTA et al. Figs. 1-2 discloses the first electrode (“An n-type electrode pad 150” ¶ [0173]) being spaced apart (“An n-type electrode pad 150 is formed on the surface of the n-type layer 121 exposed at a site where the p-type layer 123 and the active layer 122 have been partially removed.” ¶ [0173]) from the active layer (“an active layer 122” ¶ [0172]).
It would have been obvious to person having ordinary skill in the art before the effective filling date to modify n-contact arrangement of Check et al. with n-contact arrangement of HARUTA et al. for the sake of device isolation (HARUTA et al., ¶ [0235]).
Regarding Claim 2, Check et al. as modified by HARUTA et al. discloses the limitations of claim 1. Check et al. Fig. 3A further discloses, wherein the first semiconductor layer, the active layer, and the second semiconductor layer have rounded corners (“forms a mesa 50 with a mesa sidewall 50′. The mesa 50 may include the p-type layer 14, the active layer 18, and a portion of the n-type layer 16.” ¶ [0048]; Fig. 3 shows the rounded corner),
wherein the first semiconductor layer 16 has a constant width in the width direction except for the rounded corners of the first semiconductor layer 16 (Figs. 1-2 show the 16 has a constant width in the width direction except for the rounded corners of the first semiconductor layer 16).
Allowable Subject Matter
Claims 8, 10-12 and 22-23 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims and upon resolution of the 35 U.S.C. 112(b) rejection of claim 22.
REASONS FOR ALLOWANCE
The following is an examiner’s statement of reasons for allowance:
The reason for allowance of claim 8 are the prior art of record, LEE; Sang Youl (US 20210036187 A1) “LEE et al.”, SUNG; Youn Joon (US 20190013439 A1) “SUNG et al.”, Check; Michael (US 20230037469 A1) “Check et al.”, HARUTA; Yuki (US 20140103391 A1) “HARUTA et al.” SUGAWARA; Nobuhiro (US 20210320226 A1) “SUGAWARA et al.”, CHOI; Hwanjoon (US 20220238759 A1) “CHOI et al.”, and Ko; Kun Yoo (US 20070102715 A1) “Ko et al.”, alone or in combination does not teach or fairly suggest, “an inclination angle of the second side surface of the second part on the one side is equal to or substantially equal to an inclination angle of the second side surface of the second part on the another side”, in combination with other limitations of claim 6, 3, 2 and 1.
The reason for allowance of claim 10 are the prior art of record, LEE; Sang Youl (US 20210036187 A1) “LEE et al.”, SUNG; Youn Joon (US 20190013439 A1) “SUNG et al.”, Check; Michael (US 20230037469 A1) “Check et al.”, HARUTA; Yuki (US 20140103391 A1) “HARUTA et al.” SUGAWARA; Nobuhiro (US 20210320226 A1) “SUGAWARA et al.”, CHOI; Hwanjoon (US 20220238759 A1) “CHOI et al.”, and Ko; Kun Yoo (US 20070102715 A1) “Ko et al.”, alone or in combination does not teach or fairly suggest, “the second part has point symmetry shape with respect to a center of the active layer.”, in combination with other limitations of claim 6, 3, 2 and 1.
The reason for allowance of claim 11 are the prior art of record, LEE; Sang Youl (US 20210036187 A1) “LEE et al.”, SUNG; Youn Joon (US 20190013439 A1) “SUNG et al.”, Check; Michael (US 20230037469 A1) “Check et al.”, HARUTA; Yuki (US 20140103391 A1) “HARUTA et al.” SUGAWARA; Nobuhiro (US 20210320226 A1) “SUGAWARA et al.”, CHOI; Hwanjoon (US 20220238759 A1) “CHOI et al.”, and Ko; Kun Yoo (US 20070102715 A1) “Ko et al.”, alone or in combination does not teach or fairly suggest, “wherein the second side surface of the second part disposed on one side of the light emitting element is disposed on a same plane as the second side surface of one of the plurality of first parts, and wherein the second side surface of the second part disposed on the another side of the light emitting element is disposed on a same plane as the second side surface of another of the plurality of first parts.”, in combination with other limitations of claim 6, 3, 2 and 1.
The reason for allowance of claim 12 are the prior art of record, LEE; Sang Youl (US 20210036187 A1) “LEE et al.”, SUNG; Youn Joon (US 20190013439 A1) “SUNG et al.”, Check; Michael (US 20230037469 A1) “Check et al.”, HARUTA; Yuki (US 20140103391 A1) “HARUTA et al.” SUGAWARA; Nobuhiro (US 20210320226 A1) “SUGAWARA et al.”, CHOI; Hwanjoon (US 20220238759 A1) “CHOI et al.”, and Ko; Kun Yoo (US 20070102715 A1) “Ko et al.”, alone or in combination does not teach or fairly suggest, “wherein the active layer includes a third part disposed between the plurality of first parts, the third part having a third width smaller than the second width in the width direction.”, in combination with other limitations of claims 6, 3, 2 and 1.
The reason for allowance of claim 22 are the prior art of record, LEE; Sang Youl (US 20210036187 A1) “LEE et al.”, SUNG; Youn Joon (US 20190013439 A1) “SUNG et al.”, Check; Michael (US 20230037469 A1) “Check et al.”, HARUTA; Yuki (US 20140103391 A1) “HARUTA et al.” SUGAWARA; Nobuhiro (US 20210320226 A1) “SUGAWARA et al.”, CHOI; Hwanjoon (US 20220238759 A1) “CHOI et al.”, and Ko; Kun Yoo (US 20070102715 A1) “Ko et al.”, alone or in combination does not teach or fairly suggest, “wherein a third part of the active layer between the first electrode and the second electrode has a third width that is smaller than the first width of the first part and the second width of the second part.”, in combination with other limitations of claim 18.
The reason for allowance of claim 23 are the prior art of record, LEE; Sang Youl (US 20210036187 A1) “LEE et al.”, SUNG; Youn Joon (US 20190013439 A1) “SUNG et al.”, Check; Michael (US 20230037469 A1) “Check et al.”, HARUTA; Yuki (US 20140103391 A1) “HARUTA et al.” SUGAWARA; Nobuhiro (US 20210320226 A1) “SUGAWARA et al.”, CHOI; Hwanjoon (US 20220238759 A1) “CHOI et al.”, and Ko; Kun Yoo (US 20070102715 A1) “Ko et al.”, alone or in combination does not teach or fairly suggest, “wherein the active layer includes a first notched portion on a first side of the active layer and a second notched portion on a second side of the active layer, the second side being opposite to the first side, and wherein the first notched portion and the second notched portion have point symmetry with respect to a center of the active layer in a plan view.”, in combination with other limitations of claim 18.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior arts, SUGAWARA; Nobuhiro (US 20210320226 A1) “SUGAWARA et al.”, CHOI; Hwanjoon (US 20220238759 A1) “CHOI et al.”, Ko; Kun Yoo (US 20070102715 A1) “Ko et al.” made of record and not relied upon is considered pertinent to applicant’s disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to AKHEE SARKER-NAG whose telephone number is (703)756-4655. The examiner can normally be reached Monday - Friday 7:15 AM to 5:30 PM.
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/AKHEE SARKER-NAG/Examiner, Art Unit 2893
/YARA B GREEN/Supervisor Patent Examiner, Art Unit 2893
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