Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1 - 9 in the reply filed on 07/09/2026 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) were submitted on 06/14/2024 and 12/29/2025. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Response to Amendment
Applicant’s cancellation of claims 10 – 20 is acknowledged.
Applicant’s addition of claims 21 – 31 is acknowledged.
Specification
The disclosure is objected to because of the following informalities:
Paragraph [0045] states “…includes a plurality of logic active regions LM. Each of the active memory active regions AM and the logic active regions LM may include… with one of the logic active regions LM.” It appears that the logic active regions being referred to in figure 23 should be represented by the letters AL as there are no regions listed as “LM” in figure 23.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 7, and 28 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by US 20230345691 A1 hereinafter Xie.
For claim 1, Xie teaches “A semiconductor device, comprising: a first transistor (fig. 1A numeral 210) and a second transistor (fig. 1A numeral 410) sharing a first source/drain feature (fig. 1A numeral 211); a third transistor (fig. 1B numeral 220) and a fourth transistor (fig. 1B numeral 420) sharing a second source/drain feature (fig. 1B numeral 221); a first source/drain contact disposed over the first source/drain feature (fig. 8A numeral 852); a second source/drain contact disposed over the second source/drain feature (fig. 8B numeral 752); a first backside via disposed below the first source/drain feature (fig. 4A and 8A numeral 713); and a second backside via disposed below the second source/drain feature (fig. 4B and 8B numeral 731), wherein a gate structure of the first transistor is coupled to the second source/drain contact (fig. 8C shows coupling of the gate structures through cross-couple 871 and gate contacts 852 and 862 in fig. 8A – 8B; Par. [0046 - 0048]), wherein a gate structure of the fourth transistor is coupled to the first source/drain contact (Par. [0046 – 0048]).” Paragraph [0048] further describes the cross-couple structure shown in figures 9A – 9C includes connect the gate structures of the multiple transistors to the shared source/drain features.
For claim 7, Xie teaches “The semiconductor device of claim 1, wherein the first transistor comprises a first plurality of nanostructures (fig. 1A numeral 121), wherein the gate structure of the first transistor wraps around each of the first plurality of nanostructures (fig. 1A shows the gate structure comprised of 510, 511, and 512 surrounding the nanostructures 121).”
For claim 28, Xie teaches “A semiconductor device, comprising: a first transistor (fig. 1A numeral 210) and a second transistor (fig. 1A numeral 410) sharing a first source/drain feature (fig. 1A numeral 211); a third transistor (fig. 1B numeral 220) and a fourth transistor (fig. 1B numeral 420) sharing a second source/drain feature (fig. 1B numeral 221); a first source/drain contact disposed over the first source/drain feature (fig. 8A numeral 852); a second source/drain contact disposed over the second source/drain feature (fig. 8B numeral 752); a first backside via disposed below the first source/drain feature (fig. 4A and 8A numeral 713); and a second backside via disposed below the second source/drain feature (fig. 4B and 8B numeral 731), wherein a gate structure of the first transistor is coupled to the second source/drain contact (fig. 8C shows coupling of the gate structures through cross-couple 871 and gate contacts 852 and 862 in fig. 8A – 8B; Par. [0046 - 0048]), wherein a gate structure of the fourth transistor is coupled to the first source/drain contact (Par. [0046 – 0048]), wherein the first transistor comprises a first plurality of nanostructures (fig. 1A numeral 121), wherein the gate structure of the first transistor wraps around each of the first plurality of nanostructures (fig. 1A shows the gate structure comprised of 510, 511, and 512 surrounding the nanostructures 121). .” Paragraph [0048] further describes the cross-couple structure shown in figures 9A – 9C includes connect the gate structures of the multiple transistors to the shared source/drain features.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 2 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20230345691 A1 hereinafter Xie.
For claim 2, Xie teaches all of claim 1. Xie also teaches the first and second backside vias include tungsten (Par. [0040]; Par. [0045]). Xie does not explicitly state that the interface between the first backside via and the first source/drain feature and an interface between the second backside via and the second source/drain feature are free of a metal silicide. However, Xie does not teach the inclusion of metal silicide in either the backside vias or the source/drain features. It would be obvious to one of ordinary skill in the art before the effective filing date of the immediate invention that the interface between the first backside via and the first source/drain feature and an interface between the second backside via and the second source/drain feature are free of a metal silicide in Xie, as Xie does not include or teach the use of a metal silicide and teaches the use of tungsten in the first and second backside vias.
Claim(s) 3 - 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20230345691 A1 hereinafter Xie in further view of US 20210343645 A1 hereinafter Peng.
For claim 3, Xie teaches all of claim 1. Xie is silent regarding a dielectric liner disposed between the first backside via and the first source/drain feature; and a second dielectric liner disposed between the second backside via and the second source/drain feature.
Peng teaches a first and second back side via (Peng, fig. 1D numeral 115; Par. [0023]; Par. [0047]) below first and second source/drain features (fig. 1D numeral 150a and 150b). The first and second back side vias include a first and second dielectric liners (fig. 1D numeral 112).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the dielectric liners in Peng with the backside vias in Xie in order to better isolate the vias from other components and/or prevent the material of the source/drain features and the backside vias from mixing or diffusing into the layers surrounding the vias and the source/drain features.
For claim 4, Xie and Peng teach all of claim 3. Peng also teaches the first dielectric liner and the second dielectric liner comprise silicon nitride (Peng, Par. [0022]).
For claim 5, Xie and Peng teach all of claim 3. Peng also teaches the first dielectric liner extends along the sidewalls of the first backside via, and wherein the second dielectric liner extends along sidewalls of the second backside via (Peng, fig. 1D numeral 112).
Claim(s) 8 and 29 - 30 is/are rejected under 35 U.S.C. 103 as being unpatentable over US 20230345691 A1 hereinafter Xie in further view of US 20210336004 A1 hereinafter Huang.
For claim 8, Xie teaches all of claim 1. Xie is silent regarding a first resistive layer disposed between the first backside via and the first source/drain feature; and a second resistive layer disposed between the second backside via and the second source/drain feature, wherein the first resistive layer and the second resistive layer comprise tantalum silicide, zirconium silicide, chromium silicide, tantalum nitride, titanium nitride, or tungsten nitride.
Huang teaches a backside via (Huang, fig. 13B numeral 282) contacting a source/drain feature (fig. 13B numeral 260) and including a resistive layer between the backside via and the source/drain feature (fig. 13B numeral 280). The resistive layer comprises a silicide material that can include titanium, tantalum, tungsten, and other metals (Par. [0035]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the metal silicide resistive feature in Huang with the backside via in Xie in order to control the contact resistance of the source drain feature (Huang, Par. [0037]; Par. [0040]).
For claim 29, Xie teaches all of claim 28. Xie is silent regarding a first resistive layer disposed between the first backside via and the first source/drain feature; and a second resistive layer disposed between the second backside via and the second source/drain feature.
Huang teaches a backside via (Huang, fig. 13B numeral 282) contacting a source/drain feature (fig. 13B numeral 260) and including a resistive layer between the backside via and the source/drain feature (fig. 13B numeral 280).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the immediate invention to combine the metal silicide resistive feature in Huang with the backside via in Xie in order to control the contact resistance of the source drain feature (Huang, Par. [0037]; Par. [0040]).
For claim 30, Xie and Huang teach all of claim 29. Huang also teaches the first resistive layer and the second resistive layer comprise tantalum silicide, zirconium silicide, chromium silicide, tantalum nitride, titanium nitride, or tungsten nitride (Huang, (Par. [0035]).
Allowable Subject Matter
Claims 21 – 27 are allowable primarily because the references of record, alone or in combination, do not anticipate or render obvious the limitations noted therein. For example, independent claim 21’s “…and an isolation structure having a bottom portion disposed between the first backside via and the second backside via and a top portion disposed between the first source/drain feature and the second source/drain feature…”. Xie appears to teach the backside vias and transistors being separated by a gap and not having an isolation structure present between the first and second backside vias.
Claims 22 – 27 are allowable primarily as being dependent on an allowable base claim.
Any comments considered necessary by applicant MUST be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance”
Claims 6, 9, and 31 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
For claim 6, Xie, Peng, and Huang are silent regarding a first bottom isolation layer disposed between the first dielectric liner and the first source/drain feature; and a second bottom isolation layer disposed between the second dielectric liner and the second source/drain feature.
For claim 9, Xie, Peng, and Huang are silent regarding a first ferroelectric layer disposed between the first backside via and the first source/drain feature; and a second ferroelectric layer disposed between the second backside via and the second source/drain feature.
For claim 31, Xie, Peng, and Huang are silent regarding an isolation structure having a bottom portion disposed between the first backside via and the second backside via and a top portion disposed between the first source/drain feature and the second source/drain feature, wherein the first source/drain contact and the second source/drain contact partially extend into the isolation structure. Xie appears to teach the backside vias and transistors being separated by a gap and not having an isolation structure present between the first and second backside vias.
Conclusion
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/J.T.N./ Examiner, Art Unit 2815
/MONICA D HARRISON/ Primary Examiner, Art Unit 2815
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