Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Acknowledgment of Amendment
Acknowledgment is made of applicant's amendment, filed on 4/30/2026. The changes and remarks disclosed therein have been considered. Therefore, claims 1-20 remain pending in the application.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 1-16, 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over KIM PG PUB 20220139457 (hereinafter Kim).
Regarding independent claim 1, Kim teaches a device (title) comprising:
a memory array (200 in figure 6, [0070], “…a memory cell array 200…”);
a voltage driver (500 in figures 6, 13, [0070], “…voltage generator 500…”) configured to drive one of a plurality of write voltages (voltages applied to SSL, WL1-WLn, GSL or bitline in figure 12 during a write operations, Kim teaches that voltage generator 500 include a plurality of voltage generators including VPP generator 510, Va generator 520, VPGM generator 530, VPASS generator 540, and VREAD generator 550, [0106], “…During a program operation, the driving line driver 340 may supply the program voltage, the pass voltage and the read voltage from the voltage generator 500 to word-lines WL1˜WLn through driving lines S1˜Sn and the pass transistors PTP˜PTn….”) on the memory array; and
a controller (450 in figure 6) configured to select, based on a sensed characteristic of the memory array (S520 in figure 19B), one of the plurality of write voltages to drive on the memory array (figure 19B, Kim teaches a control circuit that senses an electrical characteristic of the memory array and based on that sensed characteristic, controls subsequent voltage application during program operation, [0045], “…During a sensing period, leakage of at least a portion of the target word-lines is detected by applying a fifth voltage smaller than the first voltage to the block word-line and by detecting a voltage drop of the sensing node (operation S300)...”, [0144]/[0145], “…leakage detector 570 may include a comparator…comparator 571 may compare the voltage level of the sensing node SO with the reference voltage VREF and may provide the leakage detection signal LDS…”, Kim further teaches in figure 19B that program voltage application is controlled based on the sensed result, [0156], “…the control circuit 450 increases a program voltage VPGM (operation S440) and performs the operations S530, S540 and S550 based on the increased program voltage…”).
Regarding claim 2, Kim teaches the device of claim 1, wherein the characteristic is a current, and the controller is further configured to determine that the characteristic is greater than a threshold (Kim detects leakage by observing voltage drop caused by charge sharing and current flow through word lines and pass transistors, and compares the sense voltage against a reference to determine whether leakage occurs, see [0140]-[0145], A voltage drop caused by current flow inherently reflects a current based characteristic compared toa threshold).
Regarding claim 3, Kim teaches the device of claim 1, wherein the controller is further configured to perform a pre-sensing step when performing a write operation on a memory cell of the memory array (figure 19B, Kim performs leakage detection before continuing a program operation).
Regarding claim 4, Kim teaches the device of claim 3, wherein the pre-sensing step is used to evaluate the background leakage (figure 19B, Kim performs leakage detection before continuing a program operation [0045], “…During a sensing period, leakage of at least a portion of the target word-lines is detected by applying a fifth voltage smaller than the first voltage to the block word-line and by detecting a voltage drop of the sensing node (operation S300)...”).
Regarding claim 5, Kim teaches the device of claim 1, further comprising at least one current sensor configured to sense a characteristic associated with background leakage in the memory array (Kin teaches a sensing node, leakage detector, and comparator that sense electrical behavior associated with leakage current. Under BRI, circuitry that sense voltage drop caused by current flow constitutes a current sensor).
Regarding claim 6, Kim teaches the device of claim 1, wherein: the characteristic is a first current (leakage current in S520 in figure 19B, “first current” has been interpreted as a current measured during a pre-sensing operation such as S510 that reflects leakage of the memory array before writing); and the controller is further configured to select a first or second write voltage in response to determining that the first current exceeds a first threshold (threshold used in S520 in figure 19B), and a second current (“second current” has been intercepted as a current associated with a logic state of memory cell, current in S540 in figure 19B) associated with a logic state of a memory cell of the memory array is below a second threshold (verification condition/criteria associated with S540 in figure 19B).
Regarding claim 7, Kim teaches the device of claim 1, wherein the controller is further configured to: receive a write command from a host device (write command responsible for write operation in figure 19B); and in response to receiving the write command, cause the voltage driver to apply a pre-sensing voltage to memory cells of the memory array (S510 in figure 19B, Kim teaches that during a wordline set-up period or sensing period, a pre-sensing voltage is applied to wordlines to detect leakage prior to or during a program operation); wherein the characteristic is sensed after applying the pre-sensing voltage (Kim teaches that leakage is detected after applying the sensing voltage by detecting a voltage drop at a sensing node).
Regarding claim 8, Kim teaches the device of claim 7, wherein the characteristic is associated with leakage of the memory cells (figure 19B, Kim detects leakage by observing voltage drop caused by charge sharing and current flow through word lines and pass transistors, and compares the sense voltage against a reference to determine whether leakage occurs, see [0140]-[0145]).
Regarding claim 9, Kim teaches the device of claim 1, wherein the controller is further configured to: receive a write command from a host device (command causing program start in figure 19B); and in response to receiving the write command, cause the voltage driver to apply a pre-read voltage (verify voltage used for S540 in figure 19B) to a memory cell of the memory array to determine a first logic state (initial programmed state in figure 19B) of the memory cell; and determine that the write command corresponds to a second logic state (target logic state in S540 in figure 19B) of the memory cell that is different from the first logic state (initial state of memory cells in figure 19B); wherein the memory cell is programmed to the second logic state (target logic state in S540 in figure 19B) using the selected first or second write voltage (VPGM in figure 19B).
Regarding claim 10, Kim teaches the device of claim 9, further comprising a bit line (BL in figure 8) and a word line (WL in figure 8), wherein the voltage driver is configured to drive the first or second write voltage on the memory cell by applying voltages to the bit line and word line.
Regarding claim 11, Kim teaches the device of claim 1, wherein a first write voltage of the plurality of write voltages is a default or normal write voltage (initial program voltage used on WL during a ISPP program operation, figure 19B teaches a typical ISPP program method), and a second write voltage is a boosted write voltage (step-up program voltage used on WL during a ISPP program operation).
Regarding claim 12, Kim teaches the device of claim 1, wherein the controller is further configured to: apply a pre-sensing voltage, wherein the pre-sensing voltage is applied to sense the characteristic associated with a background leakage (read voltage used at S510 in figure 19B, [0045], “…During a sensing period, leakage of at least a portion of the target word-lines is detected by applying a fifth voltage smaller than the first voltage to the block word-line and by detecting a voltage drop of the sensing node (operation S300)...”); and apply a pre-read voltage, wherein the pre-read voltage is applied to determine an existing logic state of a memory cell of the memory array (verify read voltage used at S540 in figure 19B).
Regarding independent claim 13, Kim teaches an apparatus comprising:
a memory array including memory cells (200 in figure 6, [0070], “…a memory cell array 200…”);
bias circuitry (500 in figures 6, 13, [0070], “…voltage generator 500…”) configured to apply a pre-sensing voltage (figure 19B, Kim teaches a control circuit that senses an electrical characteristic of the memory array and based on that sensed characteristic, controls subsequent voltage application during program operation, [0045], “…During a sensing period, leakage of at least a portion of the target word-lines is detected by applying a fifth voltage smaller than the first voltage to the block word-line and by detecting a voltage drop of the sensing node (operation S300)...”) to the memory cells; and
a controller (450 in figure 6) configured to determine whether a current resulting from the pre-sensing voltage exceeds a threshold (VREF in [0144]/[0145], “…leakage detector 570 may include a comparator…comparator 571 may compare the voltage level of the sensing node SO with the reference voltage VREF and may provide the leakage detection signal LDS…”, Kim further teaches in figure 19B that program voltage application is controlled based on the sensed result).
Regarding claim 14, Kim teaches the apparatus of claim 13, wherein: the bias circuitry (500 in figures 6, 13, [0070], “…voltage generator 500…”) is further configured to apply a pre-read voltage to the first memory cell (verify read in S540 in figure 19B); the controller is further configured to determine (S550 in figure 19B), based on applying the pre-read voltage, a logic state of the first memory cell.
Regarding claim 15, Kim teaches the apparatus of claim 14, further comprising sensing circuitry configured to sense a second current (current due to verify read in S540 in figure 19B) that results from applying the pre-read voltage.
Regarding claim 16, Kim teaches the apparatus of claim 15, wherein the threshold is a first threshold (VREF in [0144]/[0145]), and the sensing circuitry is further configured to determine whether the second current (current due to verify read in S540 in figure 19B) is less than a second threshold (threshold used in S540 to determine whether cell has reached target state).
Regarding independent claim 20, Kim teaches a method comprising: selecting, based on a sensed characteristic, a first write voltage or a second write voltage to drive on a memory cell of the memory array; and applying the selected first or second write voltage to the memory cell (Kim teaches an ISPP program method in figure 19B, when selected cell reaches target state, cell will be locked out from further programming by raising voltage on bitline, therefore, if one interprets “a first write voltage” or “a second write voltage” is voltage on bitline, then it reads on claim 20, or Kim teaches selecting among program voltages including initial and increased VPGM during programming operations based on detected leakage/program conditions (figure 19B, [0153]-[0157], Under BRI, the initial and increased VPGM constitute first and second write voltages selected based on sensed characteristics).
Allowable Subject Matter
Claims 17-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The closest prior art to the present invention is KIM PG PUB 20220139457 (hereinafter Kim).
Kim discloses a method of operating a nonvolatile memory device which includes at least one memory block is provided. The method includes providing a plurality of word-lines with a voltage during a word-line set-up period, precharging a plurality of driving lines with a voltage during a word-line development period, detecting a voltage drop of a sensing node during a sensing period, and detecting leakage based on the voltage drop.
Regarding claim 17 (and the respective dependent claims), the prior arts of record do not disclose or suggest the combination of all the limitations in the claim and the base claim, including: the controller is further configured to boost at least one write voltage applied to a first memory cell, in response to determining that the current exceeds the threshold.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled "Comments on Statement of Reasons for Allowance”.
Response to Arguments
Applicant's arguments have been fully considered.
Applicant argues that Kim merely teaches detecting leakage or determining data state, and does not teach “a controller configured to select, based on a sensed characteristic of the memory array, one of the plurality of write voltages to drive on the memory array”.
The argument is not persuasive.
Kim expressly teaches a control circuit 450 configured to control voltage generator 500 during program operations (figure 6, [0100]-[0102]). Kim further teaches that voltage generator 500 include multiple generated voltages including VPGM generator 530, VPASS generator 540, VREAD generator 550, VPP generator 510 and Va generator 520 (figure 13, [0101]-[0102]). During programming operations, Kim teaches supplying program voltages, pass voltages, and related operation voltages to memory cells ([0106]).
Kim additionally teaches sensing electrical characteristics associated with leakage using leakage detector 570, sensing node SO, and comparator 571 (figures 14-16, [0140]-[0145]). In particular, Kim teaches “detecting the leakage by detecting a voltage drop of the sensing node” ([0045]).
Further, Kim teaches that leakage detection is performed during a program loop (figure 19B, [0135]), determining whether leakage is detected (operation S520), performing program execution and verification operations (S530, S540), and increasing a program voltage VPGM based on detected program condition (S560, [0156], “…the control circuit 450 increases a program voltage VPGM…”)
Thus, Kim does not merely determine a data state as alleged by applicant. Rather, Kim teaches sensing electrical characteristics of the memory array and conditionally controlling subsequent program-voltage application, including increased VPGM, based on sensed conditions during program operations.
Under BRI, selectively controlling application of program voltages including increased VPGM responsive to sensed leakage/program conditions teaches or at least suggest “a controller configured to select, based on a sensed characteristic of the memory array, one of the pluralities of write voltages to drive on the memory array”, as recited in claim 1.
According, the rejection of Claim 1-16, 20 under 103 is maintained.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to XIAOCHUN L CHEN whose telephone number is (571)272-0941. The examiner can normally be reached M-F: 9AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at 571-272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/XIAOCHUN L CHEN/Primary Examiner, Art Unit 2824
Prosecution Insights