Detailed Action
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Status of Claims
The following is in response to the communication filed 6/14/2024.
Claims 1-20 are currently pending.
Claims 1-20 have been examined.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 6/14/2024, are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Claim Objections
Claim 5 objected to because of the following informalities:
Currently claim 5 reads, “at room temperature an electrical conductivity of the first material layer > the second material layer > the third material layer.” For better readability and clearer understanding of the applicants claims Examiner suggests the following amendment:
5. The hybrid bonded interface structure according to claim 4, wherein at room temperature an electrical conductivity of the first material layer is greater than the conductivity of the second material layer and the conductivity of second material is greater than the conductivity of the third material layer.
Appropriate correction is required.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 9-13, and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Theil et al. US 20230299029 A1 (hereinafter Theil).
Regarding claim 1. Theil discloses:
A hybrid bonded interface structure (Theil, Fig 1B), comprising:
a primary conduction path constructed of a first material layer; (Fig. 1B, [0038], first conductive material 16 which includes copper Cu.)
a second material layer configured to absorb stress and void reduction, arranged along a perimeter of the first material layer; and ([0038], second conductive material 18, including magnesium along a perimeter.)
a crack stop and diffusion barrier comprising a third material layer arranged along a perimeter of the second material layer, ([0029], barrier layer 12 comprises cobalt.)
wherein a Young's modulus of the third material layer is greater than a Young's modulus of the second material layer and a Young's Modulus of the first material layer. (Cobalt is known to have a Young’s Modulus of approximately 209 GPa, which is greater than the Young’s Modulus of Al (69 GPa) and the Young’s Modulus of the copper (110 GPa).)
Regarding claim 2, Theil further discloses:
an electrical conductivity of the third material layer ([0029], barrier layer 12 comprises cobalt.) is less than an electrical conductivity of the second material layer; ([0038], second conductive material 18, including magnesium along a perimeter.) and (The electrical conductivity of cobalt is about 1.7 × 10⁷ S/m and the electrical conductivity of magnesium is about 2.3 × 10⁷ S/m.)
the electrical conductivity of the second material layer ([0038], second conductive material 18, including magnesium along a perimeter.) is less than an electrical conductivity of the first material layer. ([0038], first conductive material 16 which includes copper Cu.) (The electrical conductivity of magnesium is about 2.3 × 10⁷ S/m is less than electrical conductivity of copper 5.96 × 10^7 S/m.)
Regarding claim 3, Theil further discloses:
the first material layer comprises Cu. (Fig. 1B, [0038], first conductive material 16 which includes copper Cu.)
Regarding claim 9, Theil further discloses:
a die-to-wafer or a wafer-to-wafer connection of Cu pads forming the first material layer. ([0016], the embodiment is disclosed for hybrid boding which can be used for integrating devices dies and wafters.)
Regarding claim 11, Theil discloses:
A method of forming a hybrid bonding interface (Theil, Fig 1B), the method comprising:
arranging on a dielectric (non-conductive region 10 (e.g., a non-conductive or dielectric field region)) a primary conduction path constructed of a first material layer; (Fig. 1B, [0038], first conductive material 16 which includes copper Cu. The copper conductive material making a primary conducting path.)
arranging a second material layer for stress-absorption and void reduction along a perimeter of the first material layer; and ([0038], second conductive material 18, including magnesium along a perimeter.)
arranging a crack stop and diffusion barrier comprising a third material layer along a perimeter of the second material layer, ([0029], barrier layer 12 comprises cobalt.)
wherein a Young's modulus of the third material layer is greater than a Young's modulus of the second material layer and a Young's Modulus of the first material layer. (Cobalt is known to have a Young’s Modulus of approximately 209 GPa, which is greater than the Young’s Modulus of Al (69 GPa) and the Young’s Modulus of the copper (110 GPa).)
Regarding claim 12, Theil further discloses:
the third material layer ([0029], barrier layer 12 comprises cobalt.) is selected to have an electrical conductivity less than an electrical conductivity of the second material layer; ([0038], second conductive material 18, including magnesium along a perimeter.) and (The electrical conductivity of cobalt is about 1.7 × 10⁷ S/m and the electrical conductivity of magnesium is about 2.3 × 10⁷ S/m.)
the second material layer ([0038], second conductive material 18, including magnesium along a perimeter.) is selected to have an electrical conductivity less than an electrical conductivity of the first material layer. ([0038], first conductive material 16 which includes copper Cu.) (The electrical conductivity of magnesium is about 2.3 × 10⁷ S/m is less than electrical conductivity of copper 5.96 × 10^7 S/m.)
Regarding claim 13, Theil further discloses:
Cu is arranged on the dielectric as the first material layer. (Fig. 1B, [0038], first conductive material 16 which includes copper Cu.)
Regarding claim15, Theil further discloses:
attaching the hybrid bonded interface to another hybrid bonded interface via the first material layer to form a die-to-wafer or wafer-to-wafer connection, ([0016], the embodiment is disclosed for hybrid boding which can be used for integrating devices dies and wafters.)
wherein each die or wafer includes a Cu pad as the first material layer. (Fig. 1B, [0038], first conductive material 16 which includes copper Cu.)
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Theil as applied to claim 9 above, and further in view of Seol US 20250157980 A1 (herein after Seol).
Regarding claim 10, Theil discloses all the elements of claim 9 above.
Theil further discloses:
the Cu pads ([0038], first conductive material 16 which includes copper Cu)being embedded in a dielectric material. (Fig. 1B, [0028], a non-conductive region 10 being a dielectric material.)
Theil does not specifically discloses that the dielectric material is “comprising tetraethyl orthosilicate (TEOS).”
Seol, which teaches a method of bonding semiconductor chips with insulating layers (Seol, Abstract), discloses:
a dielectric material comprising tetraethyl orthosilicate (TEOS). (Fig. 2A, [0058], support insulating layer 162a comprising TEOS).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Theil to have a dielectric material comprising TEOS as taught by Seol for purposes of providing a low-k dielectric around the interconnects.
Claims 16-17, and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Theil and Seol.
Regarding claim 16. Theil discloses:
A method of manufacturing a hybrid bonded structure, (Theil, Fig 1B)the method comprising:
depositing a crack stop and diffusion barrier material (Fig. 1B, [0029], barrier layer 12 comprises cobalt.) along an etched opening … on a dielectric material; (Fig. 1B, [0029], barrier layer 12 comprises cobalt and the interconnect is within [0028] a non-conductive region 10 being a dielectric material.)
depositing a stress-absorbing material on the crack stop and diffusion barrier; and ([0038], second conductive material 18, including magnesium along a perimeter.)
arranging on the stress-absorbing material a conductive material forming a primary conduction path, ([0038], first conductive material 16 which includes copper Cu. The copper conductive material making a primary conducting path.)
wherein a Young's modulus of the crack stop and diffusion barrier is greater than a Young's modulus of the stress-absorbing material and a Young's Modulus of the conductive material forming the primary conduction path. (Cobalt is known to have a Young’s Modulus of approximately 209 GPa, which is greater than the Young’s Modulus of Al (69 GPa) and the Young’s Modulus of the copper (110 GPa).)
Theil does not specifically disclose “an SiCN layer on a dielectric material”.
Seol, which teaches a method of bonding semiconductor chips with insulating layers (Seol, Abstract), discloses:
an SiCN layer (Fig 2A, [0049], support insulating layer 162a which is SiCN.)on a dielectric material ( [0058], support insulating layer 162a which is TEOS.)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device of Theil to have an SiCN layer on a dielectric material as taught by Seol for purposes of the overall stacking stability of a combination the support insulating layer and the front insulating layer may improve, thereby stably preventing the occurrence of delamination of the insulating layer. (Seol, [0064].)
Regarding claim 17, Theil and Seol disclose all the element of claim 16.
Theil further discloses:
arranging the conductive material on the stress-absorbing material in a form of Cu pads. (See Fig. 1B.)
Regarding claim 19, Theil and Seol disclose all the element of claim 16.
Theil further discloses:
the crack stop and diffusion barrier material ([0029], barrier layer 12 comprises cobalt.) is selected to have an electrical conductivity that is less than an electrical conductivity of the stress-absorbing material; ([0038], second conductive material 18, including magnesium along a perimeter.) and (The electrical conductivity of cobalt is about 1.7 × 10⁷ S/m and the electrical conductivity of magnesium is about 2.3 × 10⁷ S/m.)
the electrical conductivity of the stress-absorbing material ([0038], second conductive material 18, including magnesium along a perimeter.) is less than an electrical conductivity of the conductive material forming the primary conduction path. ([0038], first conductive material 16 which includes copper Cu and copper being the primary conduction path.) (The electrical conductivity of magnesium is about 2.3 × 10⁷ S/m is less than electrical conductivity of copper 5.96 × 10^7 S/m.)
Allowable Subject Matter
Claims 4-8, 14, 18, and 20 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Regarding claim 4, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a hybrid bonded interface structure comprising the third material layer comprises Cr.
Closest prior art is Lin US 8742582 B2 which teaches, semiconductor chip suited for being electrically connected to a circuit element includes a line and a bump (Lin, Abstract), and specifically teaches an adhesion/barrier layer which includes chromium, titanium, titanium-tungsten alloy, titanium nitride, tantalum, or tantalum nitride. (Lin, Col. 30, lines 35-37.) However, there is no motivation to replace the current barrier layer with the materials presented.
Claim 5 is allowable based on the dependence to claim 4.
Regarding claim 6, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a hybrid bonded interface structure comprising the third material layer is selected from a group consisting essentially of Ta, Ti and W.
Closest prior art is Lin US 8742582 B2 which teaches, semiconductor chip suited for being electrically connected to a circuit element includes a line and a bump (Lin, Abstract), and specifically teaches an adhesion/barrier layer which includes chromium, titanium, titanium-tungsten alloy, titanium nitride, tantalum, or tantalum nitride. (Lin, Col. 30, lines 35-37.) However, there is no motivation to replace the current barrier layer with the materials presented.
Regarding claim 7, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a hybrid bonded interface structure comprising the third material layer comprises Cr.
Closest prior art is Lin US 8742582 B2 which teaches, semiconductor chip suited for being electrically connected to a circuit element includes a line and a bump (Lin, Abstract), and specifically teaches an adhesion/barrier layer which includes chromium, titanium, titanium-tungsten alloy, titanium nitride, tantalum, or tantalum nitride. (Lin, Col. 30, lines 35-37.) However, there is no motivation to replace the current barrier layer with the materials presented.
Regarding claim 8, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a hybrid bonded interface structure comprising the third material layer is a metal selected from the group consisting essentially of Ta, Ti and W.
Closest prior art is Lin US 8742582 B2 which teaches, semiconductor chip suited for being electrically connected to a circuit element includes a line and a bump (Lin, Abstract), and specifically teaches an adhesion/barrier layer which includes chromium, titanium, titanium-tungsten alloy, titanium nitride, tantalum, or tantalum nitride. (Lin, Col. 30, lines 35-37.) However, there is no motivation to replace the current barrier layer in Theil with the materials presented in Lin.
Regarding claim 14, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a method of forming a hybrid bonding interface comprising Cr is arranged as the third material layer along the perimeter of the second material layer.
Closest prior art is Lin US 8742582 B2 which teaches, semiconductor chip suited for being electrically connected to a circuit element includes a line and a bump (Lin, Abstract), and specifically teaches an adhesion/barrier layer which includes chromium, titanium, titanium-tungsten alloy, titanium nitride, tantalum, or tantalum nitride. (Lin, Col. 30, lines 35-37.) However, there is no motivation to replace the current barrier layer in Theil with the materials presented in Lin.
Regarding claim 18, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a method of manufacturing a hybrid bonded structure, comprising depositing Cr as the crack stop and the diffusion barrier.
Closest prior art is Lin US 8742582 B2 which teaches, semiconductor chip suited for being electrically connected to a circuit element includes a line and a bump (Lin, Abstract), and specifically teaches an adhesion/barrier layer which includes chromium, titanium, titanium-tungsten alloy, titanium nitride, tantalum, or tantalum nitride. (Lin, Col. 30, lines 35-37.) However, there is no motivation to replace the current barrier layer in Theil with the materials presented in Lin.
Regarding claim 20, the cited prior art of record does not teach or fairly suggest, along with the other claimed features, a method of manufacturing a hybrid bonded structure, comprising the crack stop and diffusion barrier material is selected from a metal consisting essentially of Ta, Ti and W.
Closest prior art is Lin US 8742582 B2 which teaches, semiconductor chip suited for being electrically connected to a circuit element includes a line and a bump (Lin, Abstract), and specifically teaches an adhesion/barrier layer which includes chromium, titanium, titanium-tungsten alloy, titanium nitride, tantalum, or tantalum nitride. (Lin, Col. 30, lines 35-37.) However, there is no motivation to replace the current barrier layer in Theil with the materials presented in Lin.
Prior Art Considered Pertinent
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Elsherbini et al. US 20220093546 A1 – Fig. 19 shown a interconnect with copper (trace material 206) a dielectric region 218 including aluminum and magnetic region 208, which includes a magnetic material including tantalum. However the aluminum layer would have a young’s module between 320- 345 GPa depending on the composition of the dielectric. The Young’s Modulus of tantalum is 186 GPa. Therefore this doesn’t discloses: “ a Young's modulus of the third material layer is greater than a Young's modulus of the second material layer and a Young's Modulus of the first material layer
Katkar et al. US 20230132632 A1 – Fig. 2B, the conductive feature 22 ([0048] copper), conventional barrier layer 26 ([0047] transition metals (e.g., Ta, W)), and the diffusion barrier layer 24 ([0038], titanium).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to HEIM KIRIN GREWAL whose telephone number is (703)756-1515. The examiner can normally be reached Monday - Thursday 9:30 a.m. - 5:30 p.m. EST.
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/HEIM KIRIN GREWAL/Examiner, Art Unit 2812
/DAVIENNE N MONBLEAU/Supervisory Patent Examiner, Art Unit 2812
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