DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) filed on (I) June 14, 2024, (II) January 16, 2025, (III) June 12, 2025, (IV) July 29, 2025, and (V) June 12, 2026 have been considered by the examiner.
Priority
Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). The certified copy has been filed on July 22, 2024.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 19 and 20 are rejected under 35 U.S.C. 102(a)(1) and 35 U.S.C. 102(a)(2) as being anticipated by Onuma (US 2021/0043617 A1).
Claim 19, discloses a method of manufacturing a light-emitting device (image display element 200d is a light-emitting device, hereinafter, light-emitting device 200d, [0084], Fig. 7), the method comprising:
a step of growing a semiconductor crystal (compound semiconductor layer 14 includes a semiconductor crystal, [0058], Fig. 7) on a growth substrate (compound semiconductor layer 14 is grown on the drive circuit substrate 50d which is a growth substrate, hereinafter, growth substrate 50d, [0058], Fig. 7); and
a step of forming a first semiconductor layer (compound semiconductor layer 14 is a first semiconductor layer on the left-hand side, hereinafter, first semiconductor layer 14_1, [0058], Fig. 7) and a second semiconductor layer (compound semiconductor layer 14 is a second semiconductor layer to the right-hand side of the first semiconductor layer 14_1, hereinafter, second semiconductor layer 14_2, [0058], Fig. 7) by patterning the semiconductor crystal (first semiconductor layer 14_1 and second semiconductor layer 14_2 are formed by patterning the compound semiconductor layer 14 which includes a semiconductor crystal, [0058], Fig. 7), the first semiconductor layer 14_1 including a first light-emitting layer (first semiconductor layer 14_1 includes light emission layer 12 which is a first light-emitting layer, hereinafter, first light-emitting layer 12_1, [0058], Fig. 7) and having a first sidewall (first sidewall of the first semiconductor layer 14_1 is the right-hand side, hereinafter, first sidewall 14_1R, [0058], Fig. 7), the second semiconductor layer 14_2 including a second light-emitting layer (second semiconductor layer 14_2 includes light emission layer 12 which is a second light-emitting layer, hereinafter, second light-emitting layer 12_2, [0058], Fig. 7) and having a second sidewall (first sidewall 14_1R is adjacent to the left-hand side of the second semiconductor layer 14_2 which is a second sidewall of the second semiconductor layer 14_2, hereinafter, second sidewall 14_2L, [0058], Fig. 7), wherein
the first sidewall 14_1R is adjacent to the second sidewall 14_2L over a gap (first sidewall 14_1R is adjacent to the second sidewall 14_2L over a gap 60, [0058], Fig. 7), and
a normal to the first sidewall 14_1R is not parallel to a normal to the second sidewall 14_2L (a normal to the first sidewall 14_1R intersects a normal to the second sidewall 14_2L, [0058], Fig. 7).
Claim 20, discloses the method (light-emitting device 200d, [0084], Fig. 7) according to claim 19.
Onuma discloses further comprising:
a step of forming a first light-emitting element including the first semiconductor layer 14_1 (a step of forming a first light-emitting element 14_1 including the first semiconductor layer 14_1, [0058], Fig. 7) and a second light-emitting element including the second semiconductor layer 14_2 (a step of forming a second light-emitting element including the second semiconductor layer 14_2, [0058], Fig. 7); and
a step of mounting the first light-emitting element 14_1 and the second light-emitting element 14_2 to a driver substrate 50d (a step of mounting the first light-emitting element 14_1 and the second light-emitting element 14_2 to a driver substrate 50d, [0058], Fig. 7).
Allowable Subject Matter
Claims 1-18 are allowed.
The following is a statement of reasons for the indication of allowable subject matter: the closest prior art of record, Onuma (US 2021/0043617 A1), Marutani (US 2015/0137152 A1), and/or Iguchi (US 2019/0229235 A1), fails to disclose the following limitations in combination with the rest of the claim.
Regarding claim 1 (from which claims 2-18 depend), the first sidewall and the second sidewall are separated from each other by a minimum distance of from 30 nm to 2.0 µm.
Onuma discloses a light-emitting device (image display element 200d is a light-emitting device, hereinafter, light-emitting device 200d, [0084], Fig. 7) comprising:
a first semiconductor layer (compound semiconductor layer 14 is a first semiconductor layer on the left-hand side, hereinafter, first semiconductor layer 14_1, [0058], Fig. 7) including a first light-emitting layer (first semiconductor layer 14_1 includes light emission layer 12 which is a first light-emitting layer, hereinafter, first light-emitting layer 12_1, [0058], Fig. 7); and
a second semiconductor layer (compound semiconductor layer 14 is a second semiconductor layer to the right-hand side of the first semiconductor layer 14_1, hereinafter, second semiconductor layer 14_2, [0058], Fig. 7) including a second light-emitting layer (second semiconductor layer 14_2 includes light emission layer 12 which is a second light-emitting layer, hereinafter, second light-emitting layer 12_2, [0058], Fig. 7), wherein
the first semiconductor layer 14_1 has a first sidewall (first sidewall of the first semiconductor layer 14_1 is the right-hand side, hereinafter, first sidewall 14_1R, [0058], Fig. 7) adjacent to a second sidewall of the second semiconductor layer 14_2 over a gap (first sidewall 14_1R is adjacent to the left-hand side of the second semiconductor layer 14_2 which is a second sidewall of the second semiconductor layer 14_2, hereinafter, second sidewall 14_2L, [0058], Fig. 7),
a normal to the first sidewall 14_1R is not parallel to a normal to the second sidewall 14_2L (a normal to the first sidewall 14_1R intersects a normal to the second sidewall 14_2L, [0058], Fig. 7).
Onuma does not explicitly disclose the following limitation in combination with the rest of the claim; the first sidewall and the second sidewall are separated from each other by a minimum distance of from 30 nm to 2.0 µm.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Marutani (US 2015/0137152 A1) discloses in [0020], Figs. 1 and 7, a light emitting element 100 further including a light-emitting element 20 which comprises a first semiconductor layer 21, second semiconductor layer 23, and an active layer 22; wherein a normal to the first sidewall of a light-emitting element is not parallel to a normal of the second sidewall of an adjacent light-emitting element.
Iguchi (US 2019/0229235 A1) discloses in [0036] and Figs. 1A and 6C, an image display device 200 further including a plurality of adjacent light-emitting elements with various shapes.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHEVY J BOEGEL whose telephone number is (703)756-1299. The examiner can normally be reached Monday - Friday 8:00 AM - 5:00 PM.
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/CHEVY J BOEGEL/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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