DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16, 22, 23 and 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Claim 16 recites the limitation “the first luminance current.” There is insufficient antecedent basis for this limitation in the claim.
It would be unclear to one having ordinary skill in the art whether the above limitation is intended to refer to the earlier recited, “a first luminance current” (claim 15) and/or “a first luminance current” (claim 16).
Claim 22 recites the limitation “the current DAC.” There is insufficient antecedent basis for this limitation in the claim.
The claim contains no earlier recitation or limitation of a “current DAC.”
Claim 23 recites the limitation “the auxiliary switch.” There is insufficient antecedent basis for this limitation in the claim.
The claim contains no earlier recitation or limitation of an “auxiliary switch.”
Claim 26 recites the limitation “the gate capacitors.” There is insufficient antecedent basis for this limitation in the claim.
The claim contains no earlier recitation or limitation of a plurality of “gate capacitors.”
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 15-17, 19, and 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (US 2006/0114196 A1) in view of Chiou (US 2009/0091520 A1).
Regarding claim 15, Shin discloses a pixel circuit of an electroluminescence display,
wherein the electroluminescence display includes a light emitting device array [e.g., Fig. 3: 301],
which includes a plurality of light emitting devices [e.g., Fig. 4: OLED] arranged in a plurality of rows [e.g., Fig. 3: illustrated horizontal rows] and a plurality of columns [e.g., Fig. 3: illustrated vertical columns];
a plurality of pixel circuits [e.g., Fig. 4],
wherein each pixel circuit is respectively coupled to at least one corresponding light emitting device [e.g., Fig. 4: OLED],
to supply at least one corresponding display current [e.g., Paragraph 59: current from the driving transistor to the OLED] to each corresponding light emitting device [e.g., Fig. 4: OLED] according to at least one display signal [e.g., Figs. 4, 5: EMI]; and
a driver circuit [e.g., Fig. 3: 307] coupled to the plural pixel circuits to provide a first luminance current [e.g., Fig. 4: Idata] to the corresponding pixel circuit;
wherein the electroluminescence display controls the corresponding pixel circuit in a current control manner to convert the first luminance current to the display current that flows through the at least one corresponding light emitting device [e.g., Paragraph 60: The current-programming pixel driving circuit stores the voltage Vgs corresponding to the data current Idata in the program capacitor Cst and supplies the data current Idata to the, OLED by turning on the emission control transistor M3];
the pixel circuit of the electroluminescence display, comprising:
a transimpedance circuit [e.g., Fig. 4: M1, Cst], which is configured to operably convert the first luminance current to a holding voltage [e.g., Paragraph 55: a program capacitor Cst storing data current in the form of voltage; Paragraph 57: the switching transistor M2 applies a bias voltage to the gate of the driving transistor M1 to form a voltage difference between the gate and source (Vgs) of the driving transistor M1 corresponding to the data current];
a transconductance circuit [e.g., Fig. 4: M1, Cst; Paragraph 71 of the instant application discloses the transimpedance circuit and transconductance circuit are the same circuit], which is configured to operably convert the holding voltage to a second luminance current [e.g., Paragraph 56: The transistor M1 is a driving transistor that supplies the transistor M4 with the same current as the data current Idata sinking through a data line DATA[n]],
wherein the second luminance current is positively correlated with the first luminance current [e.g., Paragraph 56: The transistor M1 is a driving transistor that supplies the transistor M4 with the same current as the data current Idata sinking through a data line DATA[n]; Paragraph 74 of the instant application discloses the first luminance current and the second luminance current are equal]; and
at least one display switch [e.g., Fig. 4: M4], which is configured to operably convert the second luminance current to the corresponding display current according to the display signal, to supply the corresponding display current to the corresponding light emitting device [e.g., Paragraph 59: The transistor M4 is an emission control transistor that turns on in response to an emission control signal EMI[m] and that supplies the current from the driving transistor to the OLED] (e.g., see Paragraphs 48-91).
Shin doesn’t appear to expressly disclose providing a first luminance current to the corresponding pixel circuit according to a digital luminance signal.
However, Chiou discloses a driver circuit [e.g., Fig. 1: 100] coupled to plural pixel circuits [e.g., Fig. 2B] to provide a first luminance current [e.g., Fig. 1: Iout] to the corresponding pixel circuit according to a digital luminance signal [e.g., Fig. 1: bits b0-b3] (e.g., see Paragraphs 4-31).
Shin and Chiou are analogous art, because they are from the shared inventive field of light emitting diode display devices.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of filing to combine Chiou’s driver’s circuit with Shin’s pixel array, so as to perform a precise linear gamma curve of its digital to analog conversion without any gamma correction.
Moreover, it would have been obvious to one of ordinary skill in the art at the time of filing because all the claimed elements were known in the prior art and one skilled in the art could have combined Chiou’s driver’s circuit with Shin’s pixel array as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the filing. See KSR International Co. v. Teleflex Inc., et al., Docket No. 04-1350 (U.S. 30 April 2007).
Regarding claim 16, Chiou discloses the driver circuit includes:
a reference current source [e.g., Fig. 1: illustrated reference current IREF current source], which is configured to operably provide a reference current [e.g., Fig. 1: IREF]; and
a plurality of current DACs [e.g., Fig. 1: 112],
wherein each current DAC is configured to operably convert the reference current to a first luminance current [e.g., Fig. 1: Iout] according to the digital luminance signal,
wherein the first luminance current is positively correlated with the reference current (e.g., see Paragraph 4).
Regarding claim 17, Shin discloses the display signal includes a PWM signal [e.g., Figs. 4, 5: EMI] with a duty ratio [e.g., Fig. 5: ratio of EMI high to EMI low], and
the PWM signal is used to switch the corresponding display switch, thereby generating the display current to determine a grayscale of the corresponding light emitting device [e.g., see Paragraph 67: The data current Idata is supplied to the OLED through the emission control transistor M4 and the OLED emits light with the brightness corresponding to the data current Idata].
Regarding claim 19, Shin discloses a capacitor [e.g., Fig. 4: Cst], which is
coupled to the transimpedance circuit during a refresh period [e.g., Fig. 5: Scan low] to maintain the holding voltage and
coupled to the transconductance circuit during a display period [e.g., Fig. 5: EMI low] to provide the holding voltage to the transconductance circuit (e.g., see Paragraphs 54-77).
Regarding claim 21, Shin discloses a refresh switch [e.g., Fig. 4: M2] to couple the driver circuit to the capacitor during the refresh period according to a refresh signal [e.g., Fig. 4: Scan] to charge/discharge the capacitor to maintain the holding voltage (e.g., see Paragraphs 54-77).
Regarding claim 22, Shin discloses an auxiliary switch [e.g., Fig. 4: M3] to electrically couple a transimpedance current outflowing node [e.g., Fig. 4: node between M1 and M4] to a transimpedance control node of the transimpedance transistor of the transimpedance circuit during the refresh period, configured as a diode-connected transistor [e.g., Fig. 4: M1 is diode-connected when M2 and M3 turn on] to couple the capacitor in parallel between a first power source [e.g., Fig. 4: ELVdd] and the driver circuit to charge/discharge the capacitor to maintain the holding voltage (e.g., see Paragraphs 54-77).
Regarding claim 23, Shin discloses the auxiliary switch is turned OFF [e.g., Fig. 5: Scan high] after the refresh period, and
the capacitor is coupled to a transconductance inflow node [e.g., Fig. 4: node between M1 and M4] and a transconductance control node [e.g., Fig. 4: node between M1 and M2] of a transconductance transistor of the transconductance circuit during the display period to generate the second luminance current according to the holding voltage [e.g., Paragraph 67: when the emission control signal EMI[m] is changed from a high-level signal to a low-level signal, the emission control transistor M4 is turned on. By turning on the emission control transistor M4, the driving transistor M1 operates in the saturation region and the current Idata corresponding to the voltage Vgs stored in the program capacitor Cst is supplied to the transistor M4. The data current Idata is supplied to the OLED through the emission control transistor M4 and the OLED emits light with the brightness corresponding to the data current Idata],
wherein the transimpedance transistor and the transconductance transistor share the same transistor [e.g., Fig. 4: M1], and the refresh period and the display period do not overlap; wherein during the display period, the pixel circuit supplies the display current to the at least one corresponding light emitting device (e.g., see Paragraphs 54-77).
Claims 20 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (US 2006/0114196 A1) in view of Chiou (US 2009/0091520 A1) as applied to claim 19 above, and further in view of Kubota (US 2024/0321209 A1).
Regarding claim 20, Shin and Chiou don’t appear to expressly disclose a MOS capacitor.
However, Kubota discloses the capacitor [e.g., Fig. 3: 140] includes a gate capacitor of a MOS capacitor [e.g., Paragraph 57: a so-called MOS capacitor which is formed by interposing a gate insulating layer of a transistor between a semiconductor layer (lower electrode) and a gate electrode layer (upper electrode) of the transistor is used as the capacitive element 140].
Shin, Chiou and Kubota are analogous art, because they are from the shared inventive field of light emitting diode display devices.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of filing to combine Kubota’s MOS capacitor with Shin’s pixel circuitry, so as to provide low power consumption.
Moreover, it would have been obvious to one of ordinary skill in the art at the time of filing because all the claimed elements were known in the prior art and one skilled in the art could have combined Kubota’s MOS capacitor with Shin’s pixel circuitry as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the filing. See KSR International Co. v. Teleflex Inc., et al., Docket No. 04-1350 (U.S. 30 April 2007).
Regarding claim 26, Shin discloses during the refresh period, the electroluminescence display synchronously charges the gate capacitors [e.g., Fig. 4: Cst] corresponding to the plural light emitting devices in at least one row [e.g., Paragraphs 72-72: When the programming operation of the data current is applied, the voltages Vgs of the driving transistors of the pixels disposed in the first row of the first pixel group 3011 and in the first row of the second pixel group 3013 are stored in the program capacitors. Subsequently, when the first scan signal SCAN1[1] and the second scan signal SCAN2[1] are changed to a high level, the program capacitors of the programmed pixels hold the voltages Vgs of the driving transistors of the corresponding pixels].
Election/Restrictions
Applicant’s election of Species 2, Species 6, and Invention III in the reply filed on 9 March 2026 is acknowledged. Because applicant did not distinctly and specifically point out the supposed errors in the restriction requirement, the election has been treated as an election without traverse (MPEP § 818.01(a)).
The Applicant contends claim 18 encompasses an elected species. The Office respectfully disagrees.
Claim 18 recites, “at least one bypass current path, wherein each bypass current path and the corresponding display switch are commonly coupled to a current outflow node of the transconductance circuit to bypass the corresponding display current when the corresponding display switch is turned OFF.”
The above subject matter encompasses non-elected Species 7 or 8.
Claims 1-14, 18, 24-25 and 27-35 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to at least a nonelected species/invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9 March 2026.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The documents listed on the attached 'Notice of References Cited' are cited to further evidence the state of the art pertaining to pixel circuits.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeff Piziali whose telephone number is (571)272-7678. The examiner can normally be reached on Monday - Friday (7:30AM - 4PM). The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jeff Piziali/
Primary Examiner, Art Unit 2628
20 March 2026