DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Status of the Claims / Response to Amendment
Applicant’s amendment and remarks filed 16 June 2026 are acknowledged.
Claims 19, 21, and 22 are canceled.
Claims 15-17, 20, 23, and 26 are pending and examined herein.
Claims 1-14, 18, 24-25, and 27-35 remain withdrawn from consideration (see 16 below).
Applicant’s amendments to claims 16, 23 (re-parented to claim 15), and 26 have overcome the rejections of claims 16, 22, 23, and 26 under 35 U.S.C. 112(b) set forth in the Non-Final Office Action mailed 25 March 2026; those rejections are hereby withdrawn.
A new rejection under 35 U.S.C. 112(b), necessitated by Applicant’s amendment, is set forth below.
Claim Warning
Regarding withdrawn claims 24 and 25, the Applicant is warned of the following informalities: withdrawn claim 24 recites “The pixel circuit of the electroluminescence display of claim 22,” and claim 22 has been canceled; claim 25 depends from claim 24.
A claim which depends from a canceled claim is improper (see 37 CFR 1.75(c); MPEP § 608.01 (n)). Appropriate correction is required in any further prosecution of, or petition / rejoinder concerning, claims 24 and 25.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 15-17, 20, 23 and 26 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
As amended, claim 15 recites “a plurality of first luminance currents” (driver circuit limitation) and “a corresponding first luminance current provided to each pixel circuit” (current control limitation), but thereafter recites the singular “the first luminance current” in three places:
(i) “convert the first luminance current to a holding voltage” (transimpedance circuit limitation);
(ii) “the second luminance current is positively correlated with the first luminance current” (transconductance circuit limitation); and
(iii) “such that the first luminance current is provided to the transimpedance transistor” (final wherein clause).
There is insufficient antecedent basis for the singular “the first luminance current” in the claim, and it is unclear which of the plurality of first luminance currents is being referenced in each instance (whether each instance refers to the “corresponding” first luminance current provided to the particular pixel circuit being claimed, or otherwise).
This rejection is necessitated by Applicant’s amendment of 16 June 2026 (prior to amendment, the driver circuit limitation recited a single “first luminance current,” providing antecedent basis).
Any remaining claim(s) is/ are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being dependent upon one or more rejected base claims.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 15, 16, and 23 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (US 2006/0114196 A1) in view of Chiou (US 2009/0091520 A1).
Regarding claim 15, Shin discloses a pixel circuit of an electroluminescence display [e.g., Fig. 4: 410; Paragraph 49],
wherein the electroluminescence display includes:
a light emitting device array [e.g., Fig. 3: 301], which includes a plurality of light emitting devices [e.g., Fig. 4: OLED] arranged in a plurality of rows [e.g., Fig. 3: illustrated horizontal rows] and a plurality of columns [e.g., Fig. 3: illustrated vertical columns];
a plurality of pixel circuits [e.g., Fig. 3: pixels of 301; Fig. 4: 410],
wherein each pixel circuit is coupled to at least one corresponding light emitting device [e.g., Fig. 4: OLED, coupled via M4], and
is configured to supply, to each corresponding light emitting device of the at least one corresponding light emitting device, a corresponding display current according to a corresponding display signal [e.g., Fig. 4: EMI[m]; Paragraph 67: The data current Idata is supplied to the OLED through the emission control transistor M4]; and
a driver circuit [e.g., Fig. 3: 307; Paragraph 49: a data driving unit 307 supplying data signals to the pixels selected by the first scan signal or the second scan signal] coupled to the plurality of pixel circuits,
configured to provide a plurality of first luminance currents [e.g., Paragraph 56: the data currents Idata conveyed on the respective data lines DATA[n]] to the plurality of pixel circuits respectively
wherein the electroluminescence display controls each pixel circuit in a current control manner such that a corresponding first luminance current provided to each pixel circuit is converted to a corresponding display current that flows through the at least one corresponding light emitting device [e.g., Paragraphs 62-63, 65, 67; Paragraph 67: the current Idata corresponding to the voltage Vgs stored in the program capacitor Cst is supplied to the transistor M4];
the pixel circuit of the electroluminescence display, comprising: a transimpedance circuit [e.g., Fig. 4: M1 and Cst],
which is configured to operably convert the first luminance current to a holding voltage [e.g., Paragraph 65: Vgs of the driving transistor M1 corresponding to the data current Idata is stored in the program capacitor Cst];
a transconductance circuit [e.g., Fig. 4: M1 and Cst; the instant specification describes that the transimpedance circuit and the transconductance circuit can share the same transistor and, in an embodiment, are the same transistor (see instant Paragraphs 70, 74)],
which is configured to operably convert the holding voltage to a second luminance current [e.g., Paragraph 67],
wherein the second luminance current is positively correlated with the first luminance current [e.g., Paragraph 56: M1 supplies the transistor M4 with the same current as the data current Idata sinking through a data line; equal currents are positively correlated];
at least one display switch [e.g., Fig. 4: M4],
which is configured to operably convert the second luminance current to the corresponding display current according to the corresponding display signal [e.g., Fig. 4: EMI[m]; Paragraph 67: the emission control transistor M4 is turned on],
to supply the corresponding display current to the corresponding light emitting device [e.g., Paragraph 67];
a capacitor [e.g., Fig. 4: Cst], which is coupled to the transimpedance circuit during a refresh period to maintain the holding voltage [e.g., Paragraphs 65-66; Paragraph 66: the transistors M2 and M3 are turned off and the program capacitor Cst is charged with the voltage Vgs] and coupled to the transconductance circuit during a display period to provide the holding voltage to the transconductance circuit [e.g., Paragraph 67];
a refresh switch [e.g., Fig. 4: M2], which is configured to couple the driver circuit to the capacitor during the refresh period according to a refresh signal [e.g., Fig. 4: SCAN[m]; Paragraph 57: M2 forms a voltage path between the data line and the program capacitor Cst] to charge/ discharge the capacitor to maintain the holding voltage [e.g., Paragraphs 65-66];
Under the broadest reasonable interpretation consistent with the specification, a “refresh period” and “refresh signal” encompass a recurring period, and the signal defining it, during which the capacitor is charged or discharged so as to establish and maintain the holding voltage; the claim itself recites “charge/ discharge the capacitor to maintain the holding voltage,” and
the instant specification describes charging the capacitors during the refresh period at a rate related to capacitor leakage [instant Paragraph 70: the period of the refresh signal RFSH is related to the leakage rate of the capacitor].
Shin’s per-frame programming period, defined by the scan signal SCAN[m], is such a recurring period [e.g., Fig. 5: frame period; Paragraphs 62, 66].and an auxiliary switch [e.g., Fig. 4: M3], which is configured to electrically couple a transimpedance current outflowing node [e.g., Fig. 4: node between M1 and M4] to a transimpedance control node [e.g., Fig. 4: gate of M1] of a transimpedance transistor [e.g., Fig. 4: M1] of the transimpedance circuit during the refresh period, so as to configure the transimpedance transistor as a diode-connected transistor [e.g., Paragraph 58: M3 supplies the current from the driving transistor M1 to the data line DATA[n] at the time of programming with data current; with M2 and M3 both turned on by SCAN[m], the gate of M1 (via M2) and the drain of M1 (via M3) are electrically coupled through the data line DATA[n], configuring M1 as a diode-connected transistor];
wherein, during the refresh period, the transimpedance transistor and the capacitor are coupled in parallel between a first power source [e.g., Fig. 4: ELVdd] and [in Shin: the data-line terminal of the data driving unit 307],
such that the first luminance current is provided to the transimpedance transistor [e.g., Paragraph 62: the data current Idata sinks through the data line DATA[n], thereby forming a current path between ELVdd, the driving transistor M1, and the transistor M3], and
the capacitor is charged or discharged to maintain the holding voltage [e.g., Paragraphs 65-66].
As to the parallel coupling: with SCAN[m] at the low level, M2 couples the gate/Cst node to the data line DATA[n] [e.g., Paragraph 57] and M3 couples the drain of M1 to the data line DATA[n] [e.g., Paragraph 58].
The transimpedance transistor M1 (extending from ELVdd to its drain) and the program capacitor Cst (extending from ELVdd to the gate) thus each extend between the first power source ELVdd and the common data-line node-i.e., they are coupled in parallel between the first power source and the data-driver terminal-the data current Idata being the current of that parallel combination while Vgs is established on Cst [e.g., Paragraphs 62, 65].
This is the same manner of parallel coupling described in the instant specification, in which the first luminance current flows through the transimpedance transistor and the gate capacitance, [instant Paragraph 73: the first luminance current Igrsl to flow through the transimpedance transistor T2 and the gate capacitance T3, which are coupled between the first power source ELVDD and the current DAC 232], the coupling to the current DAC likewise being made through an enabled switch (the refresh transistor T5).
(see Paragraphs 49-67 of Shin)
Shin doesn’t appear to expressly disclose the driver circuit includes a plurality of current DACs, providing the first luminance currents according to a digital luminance signal, nor a corresponding current DAC of the plurality of current DACs as the far terminal of the recited parallel coupling.
However, Chiou discloses a data driver for an OLED display wherein the driver includes a plurality of current DACs providing output currents to a plurality of channels respectively according to a digital signal [e.g., Fig. 1: current paths (current DACs) 112, channels 1 to N, input bits b0-b3; Paragraph 4: a conventional current-type data driver in which a current mirror mirrors a multiple of the reference current IREF to each of several current paths 112, and the per-channel output current IOUT is a sum of currents flowing through the conducted current paths, the conducted paths being selected by the digital input bits b0-b3].
Each channel’s DAC output terminal constitutes the data-line-side terminal to which the corresponding pixel is coupled.
Shin and Chiou are analogous art, because they are from the shared inventive field of current-driven light emitting diode display devices and their data-driving circuitry.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of filing to implement Shin’s data driving unit 307 with Chiou’s per-channel current-DAC architecture-i.e., the simple substitution of one known current-mode data driver (Chiou’s admittedly conventional current-type data driver, [e.g., Paragraph 4]) for another (Shin’s data driving unit 307, which sinks the data currents Idata from the data lines)-so as to provide digital control of the programming current supplied on each data line.
Moreover, it would have been obvious to one of ordinary skill in the art at the time of filing because all the claimed elements were known in the prior art and one skilled in the art could have combined Chiou’s current-DAC data driver with Shin’s pixel circuitry as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the filing. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
In the combination, the parallel-coupled transimpedance transistor M1 and capacitor Cst of each pixel extend between the first power source ELVdd and the corresponding current DAC of the data driver.
Regarding claim 16, Shin in view of Chiou (as combined above) teaches the driver circuit includes:
a reference current source [Chiou Fig. 1: current source providing IREF, with current mirror 102; Paragraph 4], which is configured to operably provide a reference current; and the plurality of current DACs [Chiou Fig. 1: 112],
wherein each current DAC of the plurality of current DACs is configured to operably convert the reference current to a corresponding first luminance current according to the digital luminance signal [e.g., Paragraph 4: the mirror mirrors a multiple of the reference current IREF to each of several current paths 112, the paths conducted according to the digital input bits b0-b3],
wherein each corresponding first luminance current is positively correlated with the reference current [e.g., Paragraph 4: the output current is a sum of currents flowing through the conducted current paths, each path current being a mirrored multiple of IREF; the output is therefore positively correlated with IREF].
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Regarding claim 23, Shin discloses the auxiliary switch is turned OFF after the refresh period [e.g., Paragraph 66: the transistors M2 and M3 are turned off and the program capacitor Cst is charged with the voltage Vgs], and
the capacitor is coupled to a transconductance inflow node [e.g., Fig. 4: the ELVddside source node of M], from which the drive current flows into M1 during emission] and
a transconductance control node [e.g., Fig. 4: gate of M1] of a transconductance transistor [e.g., Fig. 4: M1] of the transconductance circuit during the display period to generate the second luminance current according to the holding voltage [e.g., Paragraph 67: the current Idata corresponding to the voltage Vgs stored in the program capacitor Cst is supplied to the transistor M4],
wherein the transimpedance transistor and the transconductance transistor share the same transistor [e.g., Fig. 4: M1 serves both roles, consistent with the shared-transistor arrangement the instant specification describes for the non-overlap mode (instant Paragraphs 70, 74)], and
the refresh period and the display period do not overlap [e.g., Fig. 5: for each row, the low (active) interval of SCAN[m] and the low (active) interval of EMI[m] are disjoint; Paragraphs 62, 66-67: the scan signal returns to the high level, and subsequently the emission control signal EMI[m] is changed to the low level];
wherein during the display period, the pixel circuit supplies the display current to the at least one corresponding light emitting device [e.g., Paragraph 67: The data current Idata is supplied to the OLED through the emission control transistor M4].
Claim 17 is rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (US 2006/0114196 A1) in view of Chiou (US 2009/0091520 A1) as applied to claim 15 above, and further in view of Kim et al (US 2019/0371231 A1).
Regarding claim 17, Shin discloses each corresponding display signal includes a signal with a duty ratio [e.g., Fig. 5: EMI[m],
a pulse signal having a ratio of its high-level duration to its low-level duration within the frame period], and the signal of the corresponding display signal is used to switch the corresponding display switch [e.g., Paragraph 67: the emission control transistor M4 is turned on],
thereby converting the second luminance current to the corresponding display current [e.g., Paragraph 67], .
Shin and Chiou don’t appear to expressly disclose the display signal’s pulse being a pulse-width-modulation (PWM) signal whose duty ratio, together with the second luminance current, determines a grayscale of the light emitting device.
However, Kim discloses driving a light emitting device of a display panel by controlling both an amplitude and a pulse width of the driving current, wherein a grayscale is expressed by the duration of light emission set by pulse-width modulation while the current amplitude is separately set [e.g., Paragraph 71: The PWM drive method is a method of expressing a grayscale or gradation according to a duration of light emission of the light emitting device 200; and even if the driving current has the same amplitude, it is possible to express various grayscales or gradations by adjusting the pulse width of the driving current and controlling the duration of light emission],
the amplitude-based and pulse-width-based drive methods being used in combination [e.g., Paragraph 70: the PAM drive method and the PWM drive method are employed together to express a grayscale or gradation] -- i.e., the grayscale is determined based on the driving current (amplitude) and the duty (pulse width) of the emission-defining signal.
Shin, Chiou and Kim are analogous art, because they are from the shared inventive field of driving light emitting diode display devices.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of filing to operate the emission control signal EMI[m] of the Shin/Chiou combination as a pulse-width-modulation signal whose duty ratio is adjusted to express the grayscale of the light emitting device, with the programmed current setting the amplitude, per Kim’s combined amplitude/ pulse-width drive scheme, so as to prevent the wavelength shift that accompanies amplitude-based grayscale control and thereby improve color reproducibility [e.g., Paragraph 4: a wavelength as well as a grayscale or gradation of light emitted is shifted together according to an amplitude of the driving current, and thereby a color reproducibility of an image is reduced; Paragraph 29: a wavelength shift according to a grayscale or gradation of an inorganic light emitting device included in a display panel can be prevented].
Moreover, it would have been obvious to one of ordinary skill in the art at the time of filing because the use of a known technique (expressing grayscale by the pulse width/ duty of the emission period at a set current amplitude, per Kim) to improve a similar device (the current-programmed pixel of Shin/Chiou, which already gates emission with the pulse signal EMI[m]) in the same way would have yielded predictable results to one of ordinary skill in the art at the time of the filing. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Claims 20 and 26 are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al (US 2006/0114196 A1) in view of Chiou (US 2009/0091520 A1) as applied to claim 15 above, and further in view of Kubota (US 2024/0321209 A1).
Regarding claim 20, Shin and Chiou don’t appear to expressly disclose the capacitor includes a gate capacitor of a MOS capacitor.
However, Kubota discloses the capacitor [e.g., Fig. 3: 140] includes a gate capacitor of a MOS capacitor [e.g., Paragraph 57: a so-called MOS capacitor which is formed by interposing a gate insulating layer of a transistor between a semiconductor layer (lower electrode) and a gate electrode layer (upper electrode) of the transistor is used as the capacitive element 140].
Shin, Chiou and Kubota are analogous art, because they are from the shared inventive field of light emitting diode display devices.
Therefore, it would have been obvious to one having ordinary skill in the art at the time of filing to combine Kubota’s MOS capacitor with Shin’s pixel circuitry, so as to provide low power consumption.
Moreover, it would have been obvious to one of ordinary skill in the art at the time of filing because all the claimed elements were known in the prior art and one skilled in the art could have combined Kubota’s MOS capacitor with Shin’s pixel circuitry as claimed by known methods with no change in their respective functions, and the combination would have yielded predictable results to one of ordinary skill in the art at the time of the filing. KSR Int’l Co. v. Teleflex Inc., 550 U.S. 398 (2007).
Regarding claim 26, Shin discloses during the refresh period, the electroluminescence display synchronously charges a plurality of capacitors corresponding to the plurality of light emitting devices in at least one row [e.g., Fig. 4: cst, per pixel; Fig. 5: SCAN1[1], SCAN2[1]; Paragraph 72: the voltages Vgs of the driving transistors of the pixels disposed in the first row of the first pixel group 3011 and in the first row of the second pixel group 3013 are stored in the program capacitors].
In the combination set forth for claim 20, each such program capacitor is implemented as a gate capacitor of a MOS capacitor per Kubota [e.g., Paragraph 57], such that the synchronously charged capacitors of the row are a plurality of gate capacitors as claimed.
Election/ Restrictions
Applicant’s election of Species 2, Species 6, and Invention III in the reply filed on 9 March 2026 was treated as an election without traverse (MPEP § 818.01(a)), as set forth in the Office Action mailed 25 March 2026.
Claims 1-14, 18, 24-25 and 27-35 remain withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to at least a nonelected species/ invention, there being no allowable generic or linking claim.
The claims as amended 16 June 2026 remain directed to the elected pixel-circuit invention and encompass the elected species (Species 2 and 6; Figs. 8A, 10, 14); no shift to a non-elected invention or species is present.
Response to Arguments
Applicant's arguments filed on 16 June 2026 have been fully considered but they are not persuasive. To the extent the arguments are directed to the claims as previously presented, they are addressed below as they pertain to the rejections of the claims as amended, set forth above.
“Refresh operation” versus “programming.”
Applicant contends that Shin’s scan-based programming of Vgs is not the claimed “refresh” operation because Shin programs a data value rather than maintaining a holding voltage.
The claim, however, recites the refresh switch coupling the driver circuit to the capacitor “to charge/ discharge the capacitor to maintain the holding voltage,” which expressly encompasses charging the capacitor;
Shin’s per-frame programming charges the program capacitor Cst with the voltage Vgs [e.g., Paragraph 66], which is then held.
Under the broadest reasonable interpretation set forth above (see the rejection of claim 15), the recurring per-frame scan period of Shin is a refresh period, and no claim language requires that the identical voltage previously held be re-written, nor that the refresh be independent of data programming.
The instant specification’s description of periodic charging related to capacitor leakage [instant Paragraph 70] is consistent with this interpretation and does not narrow the claim.
“First luminance current” distinction.
Applicant contends the claimed first luminance current differs in technical character from Shin’s Idata and Chiou’s output current because the first luminance current controls overall/average luminance while grayscale is expressed by PWM.
The distinction is not commensurate with the scope of claim 15, which requires only that the first luminance current be provided to the pixel circuit and converted, in a current control manner, to the corresponding display current; Shin’s Idata satisfies these limitations [e.g., Paragraphs 56, 62, 65, 67].
The “overall average luminance” function relied upon appears in the specification as an embodiment-level use of the digital luminance signal [instant Paragraph 61: the digital luminance signal LMN is used to adjust the overall average luminance of the light emitting device array 21 under different ambient brightness conditions] and is not recited in claim 15.
Moreover, the instant specification itself contemplates that the first and second luminance currents are equal in an embodiment [instant Paragraph 74: they are equal since the transimpedance transistor T2 and the transconductance transistor T2’ are the same transistor], undermining the contention that a current corresponding in magnitude to the display current cannot be the claimed first luminance current.
As to claim 17, where the duty-ratio-based grayscale determination is now expressly recited, a new ground of rejection over Kim is set forth above.
Chiou’s teachings.
Applicant’s characterization of Chiou (citing Paragraphs 19-23) addresses Chiou’s inventive gamma-voltage/converting-transistor embodiment.
The rejection, however, relies upon Chiou’s Figure 1 conventional current-type data driver [e.g., Paragraph 4], in which the reference current IREF is mirrored into digitally selected current paths whose sum is the per-channel output current.
A reference is prior art for all that it teaches, including the admitted-conventional arrangements it describes. The argument is therefore not persuasive as to the applied portion of Chiou.
M2/M3 coupling relationships.
Applicant contends Shin’s M2 and M3 do not disclose the recited refresh-switch and auxiliary-switch topology.
As set forth in the rejection of claim 15, M2 forms the voltage path between the data line (the driver circuit side) and the program capacitor [e.g., Paragraph 57], and M3 couples the drain of M1 to the data line at programming [e.g., Paragraph 58]; with both switches enabled, the gate and drain of M1 are electrically coupled through the data-line node, diode-connecting M1, and M1 and Cst are coupled in parallel between ELVdd and the data-driver terminal [e.g., Paragraphs 62, 65].
The term “electrically couple” under the broadest reasonable interpretation encompasses coupling through an enabled switch; the instant specification’s own arrangement couples the transimpedance transistor and capacitor to the current DAC through the enabled refresh transistor T5 [instant Paragraph 73].
The argument is therefore not persuasive.
Hindsight.
In response to applicant’s argument that the examiner’s conclusion of obviousness is based upon improper hindsight reasoning, it must be recognized that any judgment on obviousness is in a sense necessarily a reconstruction based upon hindsight reasoning, but so long as it takes into account only knowledge which was within the level of ordinary skill at the time the claimed invention was made, and does not include knowledge gleaned only from the applicant’s disclosure, such a reconstruction is proper.
The motivations articulated above are taken from the references’ own teachings (Chiou’s characterization of the Figure 1 driver as conventional; Kim’s teaching that pulse-width-based grayscale prevents the wavelength shift of amplitude-based grayscale) and not from Applicant’s disclosure.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant’s disclosure.
Kim et al (US 2020/0111404 A1) discloses, in the same family as the applied Kim et al (US 2019/0371231 A1) reference, sub-pixel driving circuits receiving a pulse amplitude modulation (PAM) data voltage and a pulse width modulation (PWM) data voltage, the PAM and PWM drive methods being employed together to express a grayscale (Paragraphs 80, 85, 116).
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeff Piziali whose telephone number is (571)272-7678. The examiner can normally be reached Monday - Friday (7:30AM - 4PM).
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Jeff Piziali/
Primary Examiner, Art Unit 2628
7 August 2026
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