Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Claims 1-20 are pending and have been examined.
Priority
Acknowledgment is made of applicant's claim for foreign benefit based on KR10-2023-0115234 filed on 08/31/2023.
Claim Rejections - 35 USC § 102
The following is a quotation of 35 U.S.C. 102(a)(1) that forms the basis for the rejection set forth in this Office action:
(a) NOVELTY; PRIOR ART.—A person shall be entitled to a patent unless—
(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention;
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 1, 4-12, 14, 18-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeon et al. (US 20210028137 A1 – hereinafter Jeon).
Regarding Claim 1, Jeon teaches a semiconductor package (see the entire document; Figs. 1A-1Q; specifically, ([0041 - [0060]), and as cited below), comprising:
a redistribution substrate ({150, 101}) that includes a redistribution pattern (150 – Fig. 1Q – [0048]) and a redistribution insulating layer (101 – [0041]);
a semiconductor chip (200 – [0060]) on the redistribution substrate ({150, 101});
a connection structure (left 110 – [0058]) that is spaced apart from the semiconductor chip (200); and
a hybrid via (120 = {120V, 120W} – [0058]) on the connection structure (left 110),
wherein the hybrid via ({120V, 120W}) comprises an inclined portion (120V – clearly shown in Fig. 1L) and an extended portion (120W) on the inclined portion (120V), and
wherein an angle between the inclined portion (120V) and an upper surface of the connection structure (top surface of 110) ranges from 50° to 75° ([0053] states θ30 is 105 to 135 degrees. Therefore, the angle between 120V and the upper surface of 110 is 45 to 130 degrees).
Regarding Claim 4, Jeon teaches the semiconductor package of claim 1, wherein a width of the extended portion in a first direction is greater than a width of a lower surface of the inclined portion in the first direction, and wherein the first direction is parallel with an upper surface of the redistribution substrate (Fig. 1L shows width of 120W is greater than the width of 120V in the x-direction. X-direction is parallel with the upper surface of the substrate).
Regarding Claim 5, Jeon teaches the semiconductor package of claim 1, wherein the connection structure (110) further comprises: a penetration connecting portion (110W) that electrically connects the hybrid via (120) and the redistribution substrate; and a connection mold layer (103 – [0051]), wherein the penetration connecting portion (110W) extends into the connection mold layer (103), wherein a width of an upper surface of the penetration connecting portion (110W) in a first direction is greater than a width of the extended portion in the first direction, and wherein the first direction is parallel with an upper surface of the redistribution substrate (Fig. 1L shows width of 110W is greater than the width of 102W).
Regarding Claim 6, Jeon teaches the semiconductor package of claim 1, wherein a width of the inclined portion (120V) in a first direction decreases as a distance to the connection structure in a second direction decreases (in the -y-direction), and wherein the first direction is parallel with an upper surface of the redistribution substrate (seen in Fig. 1L), and the second direction is perpendicular to the upper surface of the redistribution substrate (as x-direction and y-direction are perpendicular).
Regarding Claim 7, Jeon teaches the semiconductor package of claim 1, further comprising: an upper pad (left 130 – [0055]) on the hybrid via ({120V, 120W}), and a conductive pad ({140, 251} – [0058], [0060]) on the upper pad (left 130), wherein the conductive pad comprises a plurality of conductive layers (140, 251).
Regarding Claim 8, Jeon teaches the semiconductor package of claim 1, wherein the extended portion (120W) of the hybrid via extends in a first direction (y-direction) that is perpendicular to an upper surface of the redistribution substrate (since upper surface of substrate is in x-direction).
Regarding Claim 9, Jeon teaches the semiconductor package of claim 1, wherein the hybrid via ({120V, 120W}) comprises a hybrid via hole that at least partially includes a conductive material therein (120V is interpreted as a via hole with conductive as 120V is a via – see [0053]).
Regarding Claim 10, Jeon teaches a semiconductor package (see the entire document; Figs. 1A-1Q; specifically, ([0041 - [0060]), and as cited below), comprising:
a redistribution substrate ({150, 101}) that includes a redistribution pattern (150 – Fig. 1Q – [0048]) and a redistribution insulating layer (101 – [0041]);
a semiconductor chip (200 – [0060]) on the redistribution substrate ({150, 101});
a connection structure (left 110 – [0058]) that is spaced apart from the semiconductor chip (200); and
a hybrid via (120 = {120V, 120W} – [0058]) on the connection structure (left 110),
wherein the hybrid via ({120V, 120W}) comprises an inclined portion (120V – clearly shown in Fig. 1L) and an extended portion (120W) on the inclined portion (120V), wherein a width of the inclined portion (120V) in a first direction (x-direction) decreases as a distance to the connection structure in a second direction (-Y-direction) decreases (see Fig. 1Q),
wherein the first direction (x-direction) is parallel with an upper surface of the redistribution substrate (See Fig. 1Q), and the second direction is perpendicular to the upper surface of the redistribution substrate (X, Y directions are perpendicular).
Regarding Claim 11, Jeon teaches the semiconductor package of claim 10, wherein an angle between the inclined portion (120V) and an upper surface of the connection structure (top surface of 110) ranges from 50° to 75° ([0053] states θ30 is 105 to 135 degrees. Therefore, the angle between 120V and the upper surface of 110 is 45 to 130 degrees).
Regarding Claim 12, Jeon teaches the semiconductor package of claim 10, wherein the connection structure (110) further comprises: a penetration connecting portion (110W) that electrically connects the hybrid via (120) and the redistribution substrate (substrate); and a connection mold layer (103), wherein the penetration connecting portion (110W) extends into the connection mold layer (103), and wherein a width of an upper surface of the penetration connecting portion in the first direction is greater than a width of the extended portion in the first direction (Fig. 1L shows width of 110W is greater than the width of 102W).
Regarding Claim 14, Jeon teaches the semiconductor package of claim 10, further comprising an upper pad (left 130 – [0055]) on the hybrid via ({120V, 120W}), wherein a width of the upper pad (left 130) in the first direction is greater than a width of the extended portion of the hybrid via (120W) in the first direction, and wherein the width of the extended portion of the hybrid via (120W) in the first direction is greater than a width of a lower surface of the inclined portion of the hybrid via (120V) in the first direction.
Regarding Claim 18, Jeon teaches the semiconductor package of claim 10, wherein the connection structure (110) further comprises: a penetration connecting portion (110W – Fig. 1L) that electrically connects the hybrid via (120) and the redistribution substrate (substrate); and a connection mold layer (102), wherein the penetration connecting portion (110W) extends into the connection mold layer (102), and wherein a first angle between a side surface of the extended portion of the hybrid via and an upper surface of the penetration connecting portion (90 degrees as seen in Fig. 1L) is greater than a second angle between a side surface of the inclined portion of the hybrid via and the upper surface of the penetration connecting portion (second angle is less than 90 degrees as seen in Fig. 1L).
Regarding Claim 19, Jeon teaches a semiconductor package (see the entire document; Figs. 1A-1Q; specifically, ([0041 - [0063]), and as cited below), comprising:
a redistribution substrate ({110, 103} – [0058], [0059]) that includes a redistribution pattern (110) and a redistribution insulating layer (103);
a semiconductor chip (200 – [0060]) on the redistribution substrate ({110, 103});
a connection structure (left 120 = {120V, 102W}) that is spaced apart from the semiconductor chip (200);
a hybrid via (left 130 = {130V, 130W} – [0058]) on the connection structure (left 120);
a solder via (150 – [0058]) on a lower surface of the redistribution substrate ({110, 103}); and
a solder pad (400 – [0063]) on a lower surface of the solder via (150),
wherein the hybrid via (left 130) comprises an inclined portion (130V) and an extended portion (130W) on the inclined portion,
wherein the connection structure ({left 120, {104, 103}}) comprises a connection mold layer ({104, 103} – [0061]) and a penetration connecting portion (120V) that is electrically connected to the redistribution pattern (left 110),
wherein the penetration connecting portion (120V) extends into the connection mold layer (103),
wherein the connection mold layer (104, 103) is spaced apart from the semiconductor chip (200),
wherein an angle between the inclined portion of the hybrid via (130V) and an upper surface of the penetration connecting portion (upper surface of 120W) ranges from 50° to 75° ([0056] states θ40 is 105 to 135 degrees. Therefore, the angle between 130V and the upper surface of 120W is 45 to 130 degrees), and
wherein the solder pad (400), the solder via (150), the penetration connecting portion (120V), and the hybrid via (left 130) are electrically connected to each other (connections are shown in Fig. 1O).
Regarding Claim 20, Jeon teaches the semiconductor package of claim 19, wherein a width of the inclined portion (130V) in a first direction (X-direction) decreases as a distance to the connection structure in a second direction (Y-direction) decreases, and wherein the first direction (X-direction) is parallel with an upper surface of the redistribution substrate, and the second direction is perpendicular to the upper surface of the redistribution substrate (see Fig. 1O).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Notes: when present, semicolon separated fields within the parenthesis (; ;) represent, for example, as (30A; Fig 2B; [0128]) = (element 30A; Figure No. 2B; Paragraph No. [0128]). For brevity, the texts “Element”, “Figure No.” and “Paragraph No.” shall be excluded, though; additional clarification notes may be added within each field. The number of fields may be fewer or more than three indicated above. These conventions are used throughout this document.
Claims 15 is rejected under 35 U.S.C. 103 as being unpatentable over Jeon in view of Lin et al. (US 20250015069 A1 - hereinafter Lin).
Regarding Claim 15, Jeon teaches claim 14 from which claim 15 depends. Jeon further teaches a conductive pad (140 – [0058]) on the upper pad (left 130). But Jeon does not expressly disclose wherein the conductive pad includes Ni and/or Au.
In a related art, Lin teaches a conductive pad is formed of gold and nickel (Lin – [0017] – “the conductive pad 53 may be or include Au, Ag, Cu, Ni, another metal, a solder alloy”).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the claimed invention, to integrate the forming of a conductive pad of gold and/or nickel as taught by Lin into Jeon.
An ordinary artisan would have been motivated to integrate Lin structure into Jeon structure in the manner set forth above for, at least, for the obvious benefit of superior conductivity.
Allowable Subject Matter
Claims 2-3, 13, 16-17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is the Examiner’s Reasons for Allowance:
The prior art fails to disclose and would not have rendered obvious:
Regarding claim 2: The semiconductor package of claim 1, further comprising: a chip mold layer on the semiconductor chip and the connection structure; and a capping mold layer on the chip mold layer, wherein a side surface of the hybrid via is in contact with the chip mold layer and the capping mold layer.
Claim 3 depends from claim 2.
Regarding claim 13: The semiconductor package of claim 12, wherein the penetration connecting portion comprises: a first connecting portion; a second connecting portion on the first connecting portion; and a third connecting portion on the second connecting portion, wherein a width of an upper portion of the second connecting portion in the first direction is greater than a width of a lower portion of the second connecting portion in the first direction, wherein a width of the first connecting portion in the first direction is greater than the width of the lower portion of the second connecting portion in the first direction, and wherein an insulating material extends around the first connecting portion and the second connecting portion.
Regarding claim 16: The semiconductor package of claim 14, further comprising: a chip mold layer that extends around the semiconductor chip and the connection structure; and a capping mold layer on the chip mold layer, wherein the hybrid via extends into the capping mold layer and extends into the chip mold layer.
Claim 17 depends from claim 16
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMAD A. RAHMAN whose telephone number is (571) 270-0168 and email is mohammad.rahman5@uspto.gov. The examiner can normally be reached on Mon-Fri 8:00-5:00 PM.
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/MOHAMMAD A RAHMAN/
Primary Examiner, Art Unit 2898
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