DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a FINAL OFFICE ACTION in response to the Amendment/ Remarks filed 06/03/2026. Claims 1-20 are pending in the Application, of which Claims 1 and 19 are independent.
Continuity/ Priority Information
The present Application 18744887 filed 06/17/2024 claims foreign priority to INDIA, Application 202441033760, filed 04/29/2024.
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Response to Arguments
Applicant's arguments filed 06/03/2026, see Amendment/ Remarks with respect to the rejection of Claims 1-20 under 35 U.S.C. 102(a)(1) as being anticipated by Shah et al. (Pub. No. US 20190011500), have been fully considered but they are not persuasive, as set forth in the present office action.
The Examiner notes, the incorporation of the limitation “coupling an input of a non-identified scan chain to a respective scan output to reload a test pattern of the non-identified scan chain into the non-identified scan chain” in the independent Claims 1 and 19 is a new matter, which was not described in the specification as originally filed.
Applicant argues that Shah does not disclose or suggest the limitations of claim 1 as amended, "wherein while loading the respective test pattern into the identified respective scan chain, coupling an input of a non-identified scan chain to a respective scan output to reload a test pattern of the non-identified scan chain into the non-identified scan chain."
In response to Applicant arguments, in light of a new matter in claim 1, the limitation is interpreted as loading the respective test pattern into the identified respective scan chain. Flor example, Shah discloses in para. [0027] FIG. 3, multiplexors (e.g., 330, 332, 334) facilitate selection of a scan chain (e.g., 304, 306, 308, 310) i.e. corresponding to “identify a respective scan chain”, for loading either serial or parallel fashion with one another. Gates 318, 320, 322 and 324 can either mask, corresponding to non-identified scan chain, the respective chain or permit loading of the chain from a SCAN_IN port based on input from PROG_SCAN_IN. Block 314 is responsible for the compression of the test data output when scan chains are operated in parallel mode.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claims 1 and 19, the incorporation of the limitation “coupling an input of a non-identified scan chain to a respective scan output to reload a test pattern of the non-identified scan chain into the non-identified scan chain” in the independent Claims 1 and 19 is a new matter, which was not described in the specification as originally filed.
The specification fails to describe the test pattern being loaded in the non-identified scan chain. There is no illustration of a non-identified scan chain associated with the identified respective scan chain.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1 and 19, the limitation “coupling an input of a non-identified scan chain to a respective scan output to reload a test pattern of the non-identified scan chain into the non-identified scan chain” renders the Claims indefinite.
It is unclear how one is able to reload a test pattern into a non- identified scan chain which is not illustrated in the disclosure, while loading the respective test pattern into the identified respective scan chain.
Claims not specifically mentioned above are also rejected due to their dependency on a rejected claim.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Shah et al. (Pub. No. US 20190011500) Pub. Date: 2019-01-10.
Regarding independent Claims 1 and 19, Shah discloses programmable scan shift testing for a scan chain, comprising:
a critical logic circuit comprising a critical path; and a plurality of scan chains coupled to the critical logic circuit and associated with activation of the critical path; [0013] FIG. 1. The semiconductor chip 102 includes one or more function blocks 104 “critical logic circuit”, and each function block includes one or more scan chains110 for performing scan tests on the associated function block. [0015] An example portion 134 of the scan chain 110 includes a number of flip-flops (e.g., FF1, FF2, FF3) connected in series. Each of the flip-flops is provided with inputs through a corresponding multiplexor 118. [0016] When a clock pulse (CLK) is allowed to excite the scan-flops, a combinatorial logic block 126 “critical path” receives as inputs the outputs of each of the scan-flops as well as other system inputs. The combinatorial logic block 126 “critical path” then performs a combinatorial logic function on the inputs received from each one of the scan-flops to produce a logic function output.
a control circuit coupled to the plurality of scan chains configured to receive a plurality of configuration datasets, wherein each configuration dataset comprises a respective scan chain identifier and a respective test pattern, [0014] The testing system 106 includes memory 108 for storing one or more test scan patterns 114. During a test sequence referred to herein as “scan chain testing,” the test controller 112 selects test scan patterns 114 and transmits control signals to the user function block 104 for selectively programming (loading) individual elements of the scan chain 110 with values of each selected test scan pattern, as described below.
the control circuit is configured to identify a respective scan chain associated with the respective scan chain identifier, and load the respective test pattern in the identified respective scan chain. [0027] In FIG. 3, multiplexors (e.g., 330, 332, 334) are present to facilitate selection of a scan chain (e.g., 304, 306, 308, 310) i.e. corresponding to “identify a respective scan chain”, for loading either serial or parallel fashion with one another. Gates 318, 320, 322 and 324 can either mask the respective chain or permit loading of the chain from a SCAN_IN port based on input from PROG_SCAN_IN. Block 314 is responsible for the compression of the test data output when scan chains are operated in parallel mode.
Regarding Claims 2-4, 7-9, 13-16, 20, Shah discloses the scan chains are sequentially loaded with test patterns. [0015] FIG. 1. During a test mode of operation, each of the flip-flops receives data from the SI input. Each flip-flop and its corresponding multiplexor are together herein referred to as a “scan-flop” (e.g., scan-flops 128, 130, and 132). The different scan-flops 128, 130, and 132 are connected in a serial shift register fashion during a test mode such that the output of each scan-flop becomes an input to the next scan-flop when the SI input is selected.
[0016] In one implementation, a scan chain test sequence includes three phases: loading or “shift-in”, capture, and un-loading or “shift-out.” An initial loading phase is initiated by configuring the scan-flops for the test mode by asserting ‘1’ values along selection lines (SE) to selecting the SI inputs and loading one of the test scan patterns 114 (e.g., a sequence of 1's and 0's) into the scan-flops in the chain 110.
Regarding Claims 5, 6, Shah discloses wherein the activation of the critical path is enabled based on an asserted state of the mode signal.
[0016] In one implementation, a scan chain test sequence includes three phases: loading or “shift-in”, capture, and un-loading or “shift-out.” An initial loading phase is initiated by configuring the scan-flops for the test mode by asserting ‘1’ values along selection lines (SE) to selecting the SI inputs and loading one of the test scan patterns 114 (e.g., a sequence of 1's and 0's) into the scan-flops in the chain 110.
Regarding Claims 10-12, Shah discloses plurality of pattern bits is loaded in the first scan chain based on an asserted state of the first select signal; [0014] Prior to loading, values of a selected test scan pattern are decompressed by de-compression logic 116 and provided to a scan-in port 122 of the scan chain 110. In a final stage of testing for each of the test scan patterns 114, values stored in the scan chain 110 are unloaded at a scan-out port 124, compressed by the compression sub-block 120, and transmitted back to the test controller 112 for processing.
Regarding Claims 17, 18, Shah discloses logic elements that are activated based on activation bits, derived from the set of predetermined values, and wherein the plurality of critical paths are activated simultaneously. [0027] In FIG. 3, multiplexors (e.g., 330, 332, 334) are present to facilitate selection of a scan chain (e.g., 304, 306, 308, 310) for loading either serial or parallel fashion “activated simultaneously” with one another. Gates 318, 320, 322 and 324 can either mask the respective chain or permit loading of the chain from a SCAN_IN port based on input from PROG_SCAN_IN. Block 314 is responsible for the compression of the test data output when scan chains are operated in parallel mode.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: June 26, 2026
Final Rejection 20260626
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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