Prosecution Insights
Last updated: August 18, 2026
Application No. 18/745,100

PRODUCTION METHOD FOR SEMICONDUCTOR DEVICE

Non-Final OA §103§112
Filed
Jun 17, 2024
Priority
Jun 22, 2023 — JP 2023-102364
Examiner
IMTIAZ, S M SOHEL
Art Unit
Tech Center
Assignee
Sumitomo Electric Industries Ltd.
OA Round
1 (Non-Final)
91%
Grant Probability
Favorable
1-2
OA Rounds
1m
Est. Remaining
98%
With Interview

Examiner Intelligence

Grants 91% — above average
91%
Career Allowance Rate
507 granted / 559 resolved
+30.7% vs TC avg
Moderate +7% lift
Without
With
+6.9%
Interview Lift
resolved cases with interview
Typical timeline
2y 3m
Avg Prosecution
48 currently pending
Career history
579
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
62.2%
+22.2% vs TC avg
§102
17.2%
-22.8% vs TC avg
§112
18.6%
-21.4% vs TC avg
Black line = Tech Center average estimate • Based on career data from 559 resolved cases

Office Action

§103 §112
DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This office action is in response to application filed on 06/17/2024. Currently claims 1-9 are pending in the application. Information Disclosure Statement The information disclosure statement (IDS) submitted on 06/17/2024 was filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner. Claim Rejections - 35 USC § 112 (b) The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. Claim 7 is rejected under 35 U.S.C. 112(b) as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor regards as the invention. Regarding claim 7, the claim depends (through claims 6 and 5) from claim 1. Claim 1 defines “a first surface of the first nitride semiconductor layer” as the surface “exposed from the opening” that is subjected to the reduction treatment and on which the second nitride semiconductor layer is formed. Claim 5 further requires that “the first surface is a surface having N polarity.” Claim 7 then recites forming “a recess at a part of the channel layer” and states that “the first surface is an inner surface of the recess” (claim 7, lines 3–4). It is unclear how “the first surface” can simultaneously be (i) the surface exposed from the opening (claim 1), (ii) a single “surface having N polarity” (claim 5), and (iii) “an inner surface of the recess” (claim 7). An “inner surface of the recess” encompasses both the recess bottom and the recess side-wall surfaces; the side-wall surfaces of a c-plane (N-polar) nitride layer are non-polar or semi-polar crystal planes rather than N-polar surfaces, so it is indefinite whether the recited “first surface having N polarity” refers to the recess bottom only, the entire inner surface, or some other surface. The metes and bounds of the claim therefore cannot be determined. Clarification and/or correction is required. For purposes of examination, the examiner interprets “the first surface” of claim 7 in accordance with the specification (e.g., specification [0043], describing surfaces 210S/210D as the “inner surface (bottom surface and side wall surface)” of the recess) as the exposed inner surface of the recess, with the N-polarity limitation of claim 5 read on the recess bottom surface. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-4 and 8-9 is rejected under 35 U.S.C. 103 as being unpatentable over US 2019/0043978 A1 (Makabe) and further in view of US 2005/0189651 A1 (Hirose) and US 2016/0308039 A1 (Saito). Regarding claim 1, Makabe discloses, a production method for a semiconductor device (Figs. 1-3; [0018] - [0036]), the production method comprising: PNG media_image1.png 578 536 media_image1.png Greyscale forming a first nitride semiconductor layer containing gallium (a semiconductor stack S containing buffer layer 3, GaN channel layer 4, AlGaN barrier layer 5, and cap layer 6; Figs. 1-3; [0018] - [0036]), on a substrate (2); PNG media_image2.png 280 474 media_image2.png Greyscale forming a mask layer (31; Fig. 2B; [0027]) on the first nitride semiconductor layer (S); forming an opening in the mask layer (31), a part of the first nitride semiconductor layer (S) being exposed from the opening (mask 31 uses the patterned mask to expose portions of the stack and form recesses 21/22 ; Figs. 2–3; [0027] – [0028]); performing a reduction treatment of a first surface (top surface) of the first nitride semiconductor layer (S) in a chamber using a first gas mixture containing ammonia, the first surface being exposed from the opening (Fig. 3; [0030]); PNG media_image3.png 262 490 media_image3.png Greyscale forming a second nitride semiconductor layer (contact layers 7/8; Fig. 3C; [0023]) of a first conductive type (n-type) on the first surface (top surface) through metal organic chemical vapor deposition in the chamber using a second gas mixture containing hydrogen, nitrogen, ammonia, and a source material of a Group III element (Figs. 9A/10A; [0032], [0048] – [0049]); Makabe selectively grows n-type GaN contact layers 7/8, a second nitride semiconductor layer of a first, i.e., n-type, conductive type, on the exposed first surface, in the same MOCVD chamber and without air exposure, using a Ga source (TMG or TEG), ammonia (NH₃), and silane (SiH₄) as an n-type dopant source. It uses nitrogen as the carrier gas); and forming an electrode on the second nitride semiconductor layer (Figs. 1 and 6; [0024]; a source electrode 9 and a drain electrode 10 on the contact layers 7/8). But Makabe fails to teach explicitly, the reduction treatment is done in an ambient that contains hydrogen as well, However, in analogous art, Hirose discloses, the heat treatment is done in a hydrogen atmosphere (Hirose teaches that in forming ohmic contacts to a nitride (AlGaN) semiconductor, the semiconductor is subjected to a heat treatment in a hydrogen atmosphere; [0009], [0030]), Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Makabe and Hirose before him/her, to modify the teachings of a production method for the semiconductor device as taught by Makabe and to include the teachings of reduction treatment being done in an ambient containing hydrogen as taught by Hirose since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Makabe, a person with ordinary skill in the art would be motivated to reach out to Hirose while forming a production method for the semiconductor device of Makabe. But the combination of Makabe and Hirose fails to teach explicitly, the second gas mixture also contains hydrogen; However, in analogous art, Saito discloses, the second gas mixture also contains hydrogen ([0027] – [0030]; Saito teaches growing nitride layers by MOCVD - supplying hydrogen (H) as a carrier gas together with ammonia (NH₃) and TMG, and teaches selectively switching/adjusting the carrier between hydrogen and nitrogen because hydrogen increases etching of the growth surface while nitrogen suppresses it); Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Makabe, Hirose and Saito before him/her, to modify the teachings of a production method for the semiconductor device as taught by Makabe and to include the teachings of using a gas mixture of hydrogen, nitrogen, ammonia and Group-III-source as taught by Saito to control the growth rate since in MPEP 2143 (I) (A), it is stated that Combining prior art elements according to known methods to yield predictable results is obvious. Absent this important teaching in Makabe, a person with ordinary skill in the art would be motivated to reach out to Saito while forming a production method for the semiconductor device of Makabe. Regarding claim 2, Makabe discloses, the production method for the semiconductor device according to claim 1, wherein the mask layer (31) is a silicon nitride layer ([0027]). Regarding claim 3, Makabe discloses, the production method for the semiconductor device according to claim 1, wherein the second nitride semiconductor layer(7/8) is an n-type gallium nitride layer ([0023]). Regarding claim 4, Makabe discloses, the production method for the semiconductor device according to claim 1, wherein the first gas mixture contains nitrogen ([0030]). Regarding claim 8, Makabe discloses, the production method for the semiconductor device according to claim 1, wherein the second gas mixture contains triethylgallium as the source material of the Group III element ([0042]; Makabe teaches using triethylgallium as the Group III source: “tri-ethyl-gallium (TEG) may be used as a source material for gallium (Ga),” and further notes TEG lowers the growth rate and raises dopant incorporation—the same rationale recited in the application [0038]). Regarding claim 9, the combination of Makabe, Hirose and Saito discloses, the production method for the semiconductor device according to claim 1, wherein a percentage of a flow rate of nitrogen relative to a total flow rate of hydrogen and nitrogen in the second gas mixture is 30% or more and 95% or less (Makabe and Saito Ref.). The combination of Makabe and Saito uses both hydrogen and nitrogen in the regrowth ambient. The percentage of nitrogen flow relative to the total hydrogen-plus-nitrogen flow is a result-effective variable: Makabe and Saito recognize that hydrogen increases surface etching and affects mask-selectivity while nitrogen suppresses it, and applicant’s own specification [0065] characterizes this ratio as determinative of sheet resistance and surface morphology. Absent a showing of criticality or unexpected results, it would have been obvious to optimize the nitrogen percentage within the claimed 30%–95% range through routine experimentation. See MPEP 2144.05(II); In re Aller, 220 F.2d 454 (CCPA 1955) (discovery of optimum value of a result-effective variable is ordinarily within the skill of the art). Allowable Subject Matter Claims 5-7 are objected to as being dependent upon rejected base claims, but would be allowable if rewritten in independent forms including all of the limitations of the base claims and any intervening claims. Regarding claim 5, the closest prior art, US 2019/0043978 A1 (Makabe), in conjunction with US 2016/0308039 A1 (Saito) and US 2005/0189651 A1 (Hirose), and in combination with the other claimed features, fails to disclose, “the production method for the semiconductor device according to claim 1, wherein the first surface is a surface having N polarity”, in combination with the additionally claimed features, as are claimed by the Applicant. Specifically, the aforementioned ‘the production method for the semiconductor device according to claim 1, wherein the first surface is a surface having N polarity,’ is material to the inventive concept of the application at hand to achieve higher drive speed by lowering contact resistance of a nitride-semiconductor device. The core idea is to clean the exposed nitride surface inside the MOCVD chamber using a hydrogen/ammonia-containing reduction treatment, and then grow the second nitride semiconductor layer in that same chamber without air exposure. Claims 6-7 are also objected to due to their dependence on an objected base claim. Examiner’s Note (Additional Prior Arts) The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure. US 2023/0253457 A1 (Hsu) — A semiconductor device is disclosed including an epitaxial substrate. The epitaxial substrate includes a substrate. A strain relaxed layer covers and contacts the substrate. A III-V compound stacked layer covers and contacts the strain relaxed layer. The III-V compound stacked layer is a multilayer epitaxial structure formed by aluminum nitride, aluminum gallium nitride or a combination of aluminum nitride and aluminum gallium nitride. US 2022/0059528 A1 (Chiu) - A 3D semiconductor structure is disclosed including a buffer layer, a n-type high electron mobility transistor (HEMT) disposed on a first surface of the buffer layer, and a p-type high hole mobility transistor (HHMT) disposed on a second surface of the buffer layer opposite to the first surface. US 2013/0240896 A1 (Ozaki) - A nitride semiconductor layer is disclosed on a substrate. A first insulator layer is formed on the nitride semiconductor layer by steam oxidation of ALD, form a second insulator layer on the first insulator layer by oxygen plasma oxidation of ALD, form a gate electrode on the second insulator layer, and form a source and drain electrodes on the nitride semiconductor layer. The nitride semiconductor layer may include a first semiconductor layer on the substrate, and a second semiconductor layer on the first semiconductor layer. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /S M SOHEL IMTIAZ/Primary Patent Examiner Art Unit 2812 07/20/2026
Read full office action

Prosecution Timeline

Jun 17, 2024
Application Filed
Jul 23, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
91%
Grant Probability
98%
With Interview (+6.9%)
2y 3m (~1m remaining)
Median Time to Grant
Low
PTA Risk
Based on 559 resolved cases by this examiner. Grant probability derived from career allowance rate.

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