DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Election/Restriction
Applicant’s election without traverse of Species I (Claims 1-5) in the reply filed on 9/10/2026 is acknowledged.
A. Claims 6-10 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 9/10/2026.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 6/17/2024 and 3/12/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Objections
The applicant has not presented a 37 CFR 1.121(c) compliant version of the claims relative to the restriction election of 9/10/2026. The claims are, therefore, being objected to.
Claims 1-5 are objected to because of the following informalities:
A. the grammatical error “a wafer” in line 2 of claim 1. It is interpreted that for consistency with line 1 of claim 1, “a wafer” in line 2 should read as “the wafer”. Appropriate correction is required.
B. the grammatical error “the area” in line 14 of claim 1. It is interpreted that for consistency with line 7 of claim 1, “the area” in line 14 should read as “the corresponding area”. Appropriate correction is required.
In Re claims 1-5, they are objected to due to their dependence on claim 1.
C. the grammatical error “application of disturbance” in line 4 of claim 2. It is interpreted that for consistency with line 10 of claim 1, “application of disturbance” in line 4 should read as “the application of disturbance”. Appropriate correction is required.
D. the multiple grammatical errors of claim 4. It is interpreted that for clarity and consistency with claim 1, lines 3-7 of claim 4 should read as a disturbance detecting step of detecting the application of disturbance to the wafer (W) in which the plurality of areas are set in the plan view; and a disturbance-curbed operation step of independently controlling temperatures of all the areas on the basis of the detected temperature of one area to which the application of disturbance has been detected in a feedback manner when the application of disturbance has been detected. Appropriate correction is required.
E. the grammatical errors “the detected temperatures of the areas” in line 3 of claim 5; and “application of disturbance” in line 4 of claim 5. It is interpreted that for consistency with line 6 of claim 4, “the detected temperatures of the areas” in line 3 of claim 5 should read as “detected temperatures of the areas; and for consistency with line 10 of claim 1, “application of disturbance” in line 4 of claim 5 should read as “the application of disturbance”. Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claims 1-5 are rejected under 35 U.S.C. 112(b), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
A. Claim 1 recites the limitation "the corresponding area" in line 7. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, "the corresponding area" in line 7 will be interpreted to read as "a corresponding area".
B. Claim 1 recites the limitation "application of disturbance" in line 10. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, "application of disturbance" in line 10 will be interpreted to read as "an application of disturbance". And for consistency with line 10, "application of disturbance" in lines 14 and 15, will be interpreted to read as "the application of disturbance".
In Re claims 2-5, they are rejected due to their dependence on claim 1.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-5 are rejected under 35 U.S.C. 103 as being unpatentable over Mimura (US 2017/0278731 A1) in view of Abrami et al (US 5,001,423 A1, hereafter Abrami).
Re claim 1, Mimura discloses in FIG(S). 1-2 and 6-7 a temperature control device (1; [0035]) for a wafer (W; [0035]), comprising:
a mounting unit (2; [0035]) including a mounting surface (upper plane of 2) on which the wafer (W) is mountable and which is partitioned into a plurality of areas (2A/2B/2C; [0041]) in a plan view (FIG. 2B);
a temperature adjusting unit (3; [0036]) configured to independently adjust temperatures ([0004] and [0042]) of the plurality of areas (2A/2B/2C);
a temperature sensor (6; [0040]-[0041]) provided in each of the plurality of areas (2A/2B/2C) and configured to detect the temperature of a corresponding area (2A, 2B or 2C; [0041]);
a temperature control unit (24; [0042]) configured to independently control the temperatures ([0004] and [0042]) of the plurality of areas (2A/2B/2C) using the temperature adjusting unit (3);
a disturbance detecting unit (30; [0045]) configured to detect an application of disturbance (temperature difference; [0086]-[0105]) to the corresponding area (2A, 2B or 2C) on the basis of a detected temperature (temperature measurement; [0012] and [0086]-[0105]) from the corresponding temperature sensor (6 of 2A, 2B or 2C); and
a switching unit (32; [0044]) configured to feed only ([0070]-[0071] and [0086]-[0105]) the detected temperature (temperature measurement) of the temperature sensor (6) provided in the corresponding area (2A, 2B or 2C) to which the application of disturbance (temperature difference) has been detected back to the temperature control unit (3) when the application of disturbance (temperature difference) has been detected by the disturbance detecting unit (30), wherein the temperature adjusting unit (24) adjusts the temperatures (FIGS. 6-7) of the plurality of areas (2A/2B/2C) on the basis of the detected temperature (temperature measurement) fed back by the switching unit (32).
Mimura fails to disclose a plurality of temperature sensors (6) provided in each of the plurality of areas and configured to detect the temperature of the corresponding area.
However,
Abrami discloses in FIGS. 1-2 a temperature control device (1) for a wafer (5), comprising: a plurality of temperature sensors (3; col. 3, line 60 – col. 4, line 54) provided in each of a plurality of areas (2 sectors; col. 3, lines 60-66) in a 1-to-1 correspondence with a plurality of temperature adjusting elements (4; col. 3, line 60 – col. 4, line 54), and configured to detect temperatures (at 4 and measured at 6; col. 4, lines 31-54) of a corresponding area (each sector).
Thus, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the structure of Mimura by adding some of the plurality of temperature sensors of Abrami, such that a 1-to-1 correspondence exists between the plurality of temperature sensors and the plurality of temperature adjusting elements, or the plurality of temperature sensors (6) provided in each of the plurality of areas and configured to detect the temperature of the corresponding area, in order to provide a smoother temperature profile and higher cooling capacity (Abrami; col. 3, lines 39-44).
Re claim 2, England discloses the temperature control device for a wafer according to claim 1, wherein the switching unit (32) feeds the detected temperature (temperature measurement; [0012] and [0086]-[0105]) from the temperature sensor (6) provided in each of the plurality of areas (2A/2B/2C) back to the temperature control unit (24) for controlling the temperature adjusting unit (3) of the area (2A or 2B or 2C) provided with the corresponding temperature sensor (6) when the application of disturbance (temperature difference) to any (2A or 2B or 2C) of the plurality of areas (2A/2B/2C) has not been detected (no SV change at S2 in FIG. 6; [0089]).
Re claim 3, England and Abrami disclose the temperature control device for a wafer according to claim 1, wherein a plurality (all) of the temperature sensors (each 6 of England and each 3 of Abrami) are provided in each (all) of the plurality of areas (2A/2B/2C of England), and wherein the temperature control device (1) further comprises a detected temperature selecting unit (Abrami: 8; col. 4, lines 30-45) configured to select a detected temperature (temperature measurement) with a larger change in temperature per unit time (Abrami: highest temperature per number of scans; col. 4, lines 30-45) out of detected temperatures (temperature measurements) from the plurality of temperature sensors (of England and of Abrami), as part of the smoother temperature profile and higher cooling capacity discussed for claim 1.
Re claim 4, England discloses a temperature control method for the temperature control device for a wafer of claim 1, comprising: a disturbance detecting step (S2 in FIG. 6; [0089]) of detecting the application of disturbance (temperature difference) to the wafer (W) in which the plurality of areas (2A/2B/2C) are set in the plan view (FIG. 2B); and a disturbance-curbed operation step of independently controlling temperatures ([0004] and [0042]) of all the areas (2A/2B/2C) on the basis of the detected temperature (temperature measurement) of one area (2A or 2B or 2C) to which the application of disturbance (temperature difference) has been detected (in FIG. 6 and in FIG. 7; [0086]-[0105]) in a feedback manner (control loops; [0042]) when the application of disturbance (temperature difference) has been detected (SV changed at S2 in FIG. 6; [0089]).
Re claim 5, England discloses a temperature control method for the temperature control device for a wafer of claim 4, further comprising a normal operation step (from S1 to S2 to S7 in FIG. 6; [0089]) of independently controlling temperatures ([0004] and [0042]) of the plurality of areas (2A/2B/2C) on the basis of detected temperatures (temperature measurements) of the areas (2A/2B/2C) in a feedback manner (control loops; [0042]) when the application of disturbance (temperature difference) to any area (2A or 2B or 2C) of the wafer (W) has not been detected (no SV change at S2 in FIG. 6; [0089]).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
US-10096506-B2 and US-10409303-B2 disclose substrate temperature control systems comprising a plurality of temperature sensors and a plurality of thermal control elements disposed in a plurality of zones below the substrate.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ERIC W JONES whose telephone number is (408) 918-9765. The examiner can normally be reached M-F 7:00 AM - 6:00 PM PT.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, N. Drew Richards can be reached at (571) 272-1736. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/ERIC W JONES/Primary Examiner, Art Unit 2892
