Prosecution Insights
Last updated: October 22, 2026
Application No. 18/745,272

METHODS AND APPARATUS FOR COOLING DIE STACKS

Non-Final OA §102§103
Filed
Jun 17, 2024
Priority
May 30, 2024 — provisional 63/653,448
Examiner
TUTTLE, ETHAN ALEXANDER
Art Unit
2897
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Adeia Technologies Inc.
OA Round
1 (Non-Final)
0%
Grant Probability
At Risk
1-2
OA Rounds
7m
Est. Remaining
0%
With Interview

Examiner Intelligence

Grants only 0% of cases
0%
Career Allowance Rate
0 granted / 2 resolved
-68.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
2y 12m
Avg Prosecution
28 currently pending
Career history
29
Total Applications
across all art units

Statute-Specific Performance

§103
55.9%
+15.9% vs TC avg
§102
32.2%
-7.8% vs TC avg
§112
11.9%
-28.1% vs TC avg
Black line = Tech Center average estimate • Based on career data from 2 resolved cases

Office Action

§102 §103
Detailed Action Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim(s) 53-55, 64-65, 69, and 71 is/are rejected under 35 U.S.C. 102(a)(1) and (a)(2) as being anticipated by Chainer (Pub. No. US20170186728 A1). Regarding claim 53, Chainer further teaches a heat pipe device comprising: a phase change fluid; and a monolithic structure having at least one cavity housing the phase change fluid, wherein the monolithic structure is disposed over a first die and below a second die (Figs. 8 and 9, thermal cooling unit 806, microchannel coolers 820, dies 104,108; ¶54-55). Regarding claim 54, Chainer further teaches the monolithic structure comprises silicon (thermal cooling unit 106; ¶69). Regarding claim 55, Chainer further teaches a plurality of interconnects extending through the monolithic structure and electrically connecting the first die and the second die (Figs. 8 and 9, TSVs 816, thermal cooling unit 806, dies 104,108; ¶54-55). Regarding claim 64, Chainer further teaches an electronics package comprising: a first die (Fig. 2, die 104; ¶33); a semiconductor element disposed over the first die, the semiconductor element comprising at least one cavity (Fig. 2, thermal cooling unit 106, fluid channels 120; ¶32-33, 69); a second die disposed over the semiconductor element (Fig. 2, die 108; ¶33); and a plurality of vias extending through the semiconductor element from the first die to the second die (Fig. 2, TSVs 116, thermal cooling unit 106, dies 104,108; ¶33). Regarding claim 65, Chainer further teaches the semiconductor element is a cooling element (Figs. 2 and 3, thermal cooling unit 106; ¶33-42). Regarding claim 69, Chainer further teaches the cooling element comprises a first substrate and a second substrate (Fig. 16, die halves 1601, 1603; ¶69-70). Regarding claim 71, Chainer further teaches the cooling element comprises two or more cavities, wherein the two or more cavities are separated by one or more wall structures extending along a length of the cooling element and extending from a bottom surface of the cooling element to a top surface of the cooling element (Figs. 2-5, thermal cooling unit 106, fluid channels 120, TSVs 116, thermal cooling unit 406, microchannel coolers 420, TSVs 416; ¶32-48). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. Claim(s) 1, 5, 15, 17, 60, and 66 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chainer in view of Liu et al. (Pub. No. US 20250201651 A1). Regarding claim 1, Chainer teaches an electronics package comprising: a first die (Fig. 2, die 104; ¶33); a cooling element disposed over the first die, the cooling element comprising at least one cavity (Fig. 2, thermal cooling unit 106, fluid channels 120; ¶32-33); a second die disposed over the cooling element (Fig. 2, die 108; ¶33); and a plurality of vias extending through the cooling element from the first die to the second die (Fig. 2, TSVs 116, dies 104,108, thermal cooling unit 106; ¶33). However, Chainer does not explicitly teach having a wicking layer disposed over an interior surface of the at least one cavity. Liu teaches a cooling element having a wicking layer disposed over an interior surface of the at least one cavity (Fig. 3, first VC heat spreader 210, wick layer 215; ¶42-46). Chainer and Liu are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the cooling element of Chainer with the teachings of Liu such that the cooling element has a wicking layer disposed over an interior surface of the at least one cavity. For the purpose of using capillary action to move the cooling fluid around in the device, as recognized by Liu. Regarding claim 5, Chainer further teaches the cooling element comprises two or more cavities, wherein the two or more cavities are separated by one or more wall structures extending along a length of the cooling element and extending from a bottom surface of the cooling element to a top surface of the cooling element, and wherein the plurality of vias extends through the one or more wall structures and electrically connects the first and second dies (Figs. 2-5, thermal cooling unit 106, fluid channels 120, TSVs 116, thermal cooling unit 406, microchannel coolers 420, TSVs 416; ¶32-48). Regarding claim 15, Chainer further teaches the cooling element comprises one open cavity having one or more pillar structures extending through the cooling element, wherein the plurality of vias extends through the pillar structures and electrically connects the first and second dies (Figs. 4 and 5, thermal cooling unit 406, microchannel coolers 420, TSVs 416; ¶43-48). Regarding claim 17, Chainer further teaches the at least one cavity comprises a fluid having a boiling point in a range of approximately 50°C and approximately 150°C (microchannel coolers 120, 420, 620, 820, 1020, 1120, 1220; ¶72). Regarding claim 60, Chainer teaches the heat pipe of claim 53, however Chainer does not explicitly teach a wicking layer disposed over an interior surface of the at least one cavity. Liu teaches a wicking layer disposed over an interior surface of the at least one cavity (Fig. 3, first VC heat spreader 210, wick layer 215; ¶42-46). Chainer and Liu are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the cooling element of Chainer with the teachings of Liu such that the cooling element has a wicking layer disposed over an interior surface of the at least one cavity. For the purpose of using capillary action to move the cooling fluid around in the device, as recognized by Liu. Regarding claim 66, Chainer teaches the electronics package of claim 65, however Chainer does not explicitly teach the cooling element comprises the at least one cavity having a wicking layer disposed over an interior surface of the at least one cavity. Liu teaches the cooling element comprises the at least one cavity having a wicking layer disposed over an interior surface of the at least one cavity (Fig. 3, first VC heat spreader 210, wick layer 215; ¶42-46). Chainer and Liu are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the cooling element of Chainer with the teachings of Liu such that the cooling element comprises the at least one cavity having a wicking layer disposed over an interior surface of the at least one cavity. For the purpose of using capillary action to move the cooling fluid around in the device, as recognized by Liu. Claim(s) 2 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chainer in view of Liu as applied to claim 1 above, and further in view of Mongia et al. (Pub. No. US 20250140741 A1), hereinafter referred to as Mongia. Regarding claim 2, Chainer further teaches the cooling element comprises a first substrate and a second substrate, and wherein the first substrate is bonded to the second substrate (Fig. 16, die halves 1601, 1603; ¶69-70). However, Chainer in view of Liu does not explicitly teach the substrate being directly bonded. Mongia teaches direct bonding between interconnects and IC dies (Figs. 1B and 1C, interconnect 140, IC dies 104a,104b; ¶94-96). Chainer, Liu, and Mongia are all analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the cooling element of Chainer in view of Liu with the teaching of Mongia such that the first substrate is directly bonded to the second substrate. For the purpose of forming strong bonds between elements in the device without the need for an intervening adhesive. Regarding claim 10, Chainer in view of Liu does not explicitly teach the plurality of vias have a pitch in a range of 1 µm to 200 µm. Mongia teaches the plurality of vias have a pitch in a range of 1 µm to 200 µm (interconnects 140, ¶68, 96). Chainer, Liu, and Mongia are all analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the TSVs of Chainer in view of Liu with the teaching of Mongia such that the plurality of vias have a pitch in a range of 1 µm to 200 µm. For the purpose of having high density interconnects which can have benefits such as high bandwidth, low latency, and compact chip packages. Claim(s) 11-13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chainer in view of Liu as applied to claim 1 above, and further in view of Hsu et al. (US Patent No. 12,087,664), hereinafter referred to as Hsu. Regarding claim 11, Chainer in view of Liu does not explicitly teach at least one dummy die comprising a connecting cavity in fluid communication with the at least one cavity of the cooling element. Hsu teaches at least one dummy die comprising a connecting cavity in fluid communication with the at least one cavity of the cooling element (Figs. 11 and 12, dummy layer 60, channel 620, lid 30, coolant 40, liquid inlet 322, liquid outlet 324; Col. 7, line 22 – Col. 8, line 21). Chainer, Liu, and Hsu are all analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the cooling element of Chainer in view of Liu with the teaching of Hsu such that there is at least one dummy die comprising a connecting cavity in fluid communication with the at least one cavity of the cooling element. For the purpose of cooling and heat management of semiconductor chips and packages, as recognized by Hsu. Regarding claim 12, Chainer further teaches an upper cooling element over the second die, the upper cooling element in fluid communication with the connecting cavity (Figs. 11 and 12, thermal cooling units 1106-2, 1206-2, die 108, front manifold 1124, 1224, back manifold 1126, 1226; ¶58-62). However, Chainer does not explicitly teach the upper cooling element including an expansion chamber. Liu teaches the upper cooling element including an expansion chamber (Figs. 1, 3 and 9, first VC heat spreader 210, vapor-chamber 213; ¶42-46, 69). Chainer, Liu, and Hsu are all analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the cooling element of Chainer with the teaching of Liu such that the upper cooling element includes an expansion chamber. For the purpose of cooling the device using a two-phase vaporizable liquid to cool the device, as recognized by Liu. Regarding claim 13, Chainer does not explicitly teach a heat sink disposed over and coupled to the upper cooling element. Liu teaches a heat sink disposed over and coupled to the upper cooling element (Fig. 1, first VC heat spreader 210, heat sink 230; ¶59). Chainer, Liu, and Hsu are all analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the cooling element of Chainer with the teaching of Liu such that there is a heat sink disposed over and coupled to the upper cooling element. For the purpose of using a heat sink improve the heat dissipation efficiency of the cooling element, as recognized by Liu. Claim(s) 59 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chainer in view of Bernstein et al. (Pub. No. US 20090108435 A1), hereinafter referred to as Bernstein. Regarding claim 59, Chainer teaches the heat pipe device of claim 53. However, Chainer does not explicitly teach a portion of the heat pipe device disposed over the first die and below the second die has thickness of approximately 50 µm or less. Bernstein teaches a portion of the heat pipe device disposed over the first die and below the second die has thickness of approximately 50 µm or less (Figs. 5 and 6, chip stack 110, fluid channel 175; ¶63). Chainer and Bernstein are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the cooling element of Chainer with the teachings of Bernstein such that a portion of the heat pipe device disposed over the first die and below the second die has thickness of approximately 50 µm or less. Claim(s) 70 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chainer in view of Mongia. Regarding claim 70, Chainer teaches the electronics package of claim 69, however Chainer does not explicitly teach a hybrid bond, wherein the hybrid bond is between the first substrate and the second substrate Mongia teaches a hybrid bond, wherein the hybrid bond is between the first substrate and the second substrate (Figs. 1B and 1C, interconnect 140, IC dies 104a,104b; ¶94-96). Chainer and Mongia are analogous art as they are in the same field of endeavor of semiconductor devices. Therefore, it would have been obvious to one of ordinary skill before the effective filing date of the claimed invention to modify the cooling element of Chainer with the teaching of Mongia such that the device has a hybrid bond, wherein the hybrid bond is between the first substrate and the second substrate. For the purpose of forming strong bonds between elements in the device without the need for an intervening adhesive. Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Andry et al. (US Patent No. 11,127,715). Any inquiry concerning this communication or earlier communications from the examiner should be directed to ETHAN ALEXANDER TUTTLE whose telephone number is (571)272-7055. The examiner can normally be reached Monday - Friday, 9 am - 5 pm ET. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached at 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /FERNANDO L TOLEDO/Supervisory Patent Examiner, Art Unit 2897 /E.A.T./ Examiner, Art Unit 2897
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Prosecution Timeline

Jun 17, 2024
Application Filed
Oct 01, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
0%
Grant Probability
0%
With Interview (+0.0%)
2y 12m (~7m remaining)
Median Time to Grant
Low
PTA Risk
Based on 2 resolved cases by this examiner. Grant probability derived from career allowance rate.

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