Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the vertical stack of the peripheral circuits of claim 6-10 and 16-19 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Figure 1 does not show a vertical stack of peripheral circuits figure 3 point to element 310 but there is no indication of what constitutes a peripheral circuit the bit lines must be between these circuits but only the layer is depicted no individual peripheral circuit is depicted. Without knowing the structure of a peripheral circuit on cannot determine when a first bit line interconnection structure is coupled between the peripheral circuits
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable Lee 20250107099.
a. As to claim 11 applicant has not set forth a “vertical direction” Lee therefore teaches figures 3 and 4, as oriented below so that the vertical direction is as provided with the top of the page,: a first semiconductor stack comprising: a first transistor layer comprising an array of first vertical transistors (SP1 with WL1 and BG1), each first vertical transistor, and a first storage layer vertically stacked on the first transistor layer and comprising an array of first capacitors each comprising a high-K dielectric material between two conductive layers and being coupled with a corresponding one of the array of the first vertical transistors (CAP1 paragraph 33 specifically aluminum oxide, hafnium oxide, and zirconium oxide); and a second semiconductor stack being vertically stacked on the first semiconductor stack (items sp2 with BG2 WL2), and comprising: a second transistor layer comprising an array of second vertical transistors (each sp2 BG2 WL2), and a second storage layer being vertically stacked on the second transistor layer and comprising an array of second capacitors each comprising a ferroelectric material between two conductive layers and being coupled with a corresponding one of the array of the second vertical transistors (CAP2 item DL2 paragraph 21).
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Lee does not explicitly teach that DL1 must be aluminum oxide, hafnium oxide, and zirconium oxide, all are high-k dielectrics, and DL2 must be a ferroelectric.
However, applicant has shown no unexpected results and the materials are suggested by Lee.
Thus, it would have been obvious to one of ordinary skill in the art at the time of filing to form DL1 as be aluminum oxide, hafnium oxide, and zirconium oxide and DL2 as a ferro electric to use conventional material to provide expected out comes of varying volatile memory as suggest by Lee paragraph 4 with the desired response out comes.
b. As to claim 12, Lee teaches he second storage layer comprises more than one layer of second capacitors there are multiple capacitor layers for CAP2 one associated with a first set of SP2 below the capacitors a depicted and another above the other set of capacitors as depicted.
Allowable Subject Matter
Claims 1-10 and 20 are allowed.
Closest prior art Jing 20240121942 Xiao 20230019891 Zhu 20230320071 teach multi-level drams including on each level a vertical transistor . Jing Figure 15 of Jing item 310 has a top and bottom dram layer each layer including a separate vertical transistor (reference to figure 12 showing the transistor structure.
Xiao, figure 1, also teaches a multiple dram level (100s ) including in each layer a vertical tft item 102 and corresponding capacitors item 146. Each capacitor is made up of composite dielectrics but each level has the composite (see e.g. figure 2 items 156 166 176) thus the capacitor dielectric from layer to layer is the same.
Zhu figure 4 teaches multiple vertical tft layers coupled to different capacitors figures 2 and 3.
Prior art does not teach and or suggest for claims 1 and 20 and a different material provided for the first vertical 9999transistor group relative the second vertical transistor.
Claims 13-19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
For same reasons as claim 1 claim 13 is allowed since prior art does not teach and or suggest each first vertical transistor comprising a first vertical channel structure comprising a first material; and each second vertical transistor comprising a second vertical channel structure comprising a second material different from the first material; as discussed in relation to claim 1.
As to claim 16, prior art fails to teach and or suggest a peripheral circuit layer comprising peripheral circuits and being vertically stacked with the first semiconductor stack and the second semiconductor stack. Here being vertically stacked refers to the peripheral circuit layer which would be horizontally adjacent based on the perspective the office’s interpretation takes.
Relevant Yamazaki 20260052673 teaches a memory cell (figure 29) comprising a MIM capacitor (lower structure items 115-130) and upper capacitor (top capacitor 230-250) including an oxide material ( and item 230) and a second insulator item 250) Yamazaki does not teach two stacks of transistors as required by claim 11.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MATTHEW L REAMES whose telephone number is (571)272-2408. The examiner can normally be reached M-Th 6:00 am-4:00 pm EST.
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/MATTHEW L. REAMES/
Primary Examiner
Art Unit 2896
/MATTHEW L REAMES/Primary Examiner, Art Unit 2896
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