Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 8, 9, 13 - 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Marin (US 20210014972).
Regarding claim 8, Marin discloses an interposer comprising:
a first via (the via 170, 171, 172; Fig. 1A & 1B) including a first via hole (the via hole of 170 - 172) formed to be extended in a height direction of the interposer and a first plating layer (the plated via hole PTH; paragraph 21) disposed on at least a part of an inside of the first via hole;
a second via (via 180a, 180b, 182a, 182b) including a second via hole (via hole of 180a, 180b, 182a, 182b) formed to be extended in the height direction of the interposer and having a diameter being increased toward a direction getting away from the first via (Fig. 1A & 1B) and a second plating layer (the plated via hole PTH; paragraph 21) disposed on an inside of the second via hole and coming in contact with at least a part of the first plating layer, and disposed at one end of the first via;
a third via (the via 181a, 181b, 183a, 183b) including a third via hole (the via hole of 181a, 181b, 183a, 183b) formed to be extended in the height direction of the interposer and having a diameter being increased toward the direction getting away from the first via and a third plating layer (the plated via hole PTH; paragraph 21) disposed on an inside of the third via hole and coming in contact with the at least a part of the first plating layer, and disposed at the other end of the first via;
a first pad (120a) surrounding at least a part of an outside of the second via hole (321) and disposed vertically to the height direction of the interposer; and a second pad (120b) surrounding at least a part of an outside of the third via hole (331) and disposed vertically to the height direction of the interposer.
Regarding claim 9, Marin discloses the claimed invention as set forth in claim 8. Marin further suggests the first via is formed so that a width of the first via (172, Fig. 1B) is larger than a width of one end of the second via (182a) and a width of one end of the third via (183a).
Regarding claim 13, Marin discloses the claimed invention as set forth in claim 8. Marin further suggests the first plating layer is disposed along an inner periphery of the first via hole with a thickness (170, Fig. 1B), and wherein the first via further includes an inner layer disposed in an inside direction of the first plating layer (the resin layer similar to 175; fig. 1A).
Regarding claim 14, Marin discloses the claimed invention as set forth in claim 8. Marin further suggests a copper foil (the via and pad are made of copper; paragraph 30; Fig. 3A), wherein at least a part of the copper foil is disposed on an outside of the first via hole (the top and bottom layer of the via 375 are layers of copper) at one end and the other end of the first via hole.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1, 2, 6, 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marin (US 20210014972), in view of Leopold (US 20210014972).
Regarding claim 1, Marin discloses an electronic device comprising:
the interposer includes: a first via (the via 170, 171, 172; Fig. 1A & 1B) including a first via hole (the via hole of 170 - 172) formed to be extended in a height direction of the interposer and a first plating layer (the plated via hole PTH; paragraph 21) disposed on at least a part of an inside of the first via hole;
a second via (via 180a, 180b, 182a, 182b) including a second via hole (via hole of 180a, 180b, 182a, 182b) formed to be extended in the height direction of the interposer and having a diameter being increased toward a direction getting away from the first via (170 - 172) and a second plating layer (the plated via hole; paragraph 21) disposed on an inside of the second via hole and coming in contact with at least a part of the first plating layer (Fig. 1A – 1B), and disposed at one end of the first via (170 - 172);
a third via (the via 181a, 181b, 183a, 183b) including a third via hole (the via hole of 181a, 181b, 183a, 183b) formed to be extended in the height direction of the interposer and having a diameter being increased toward the direction getting away from the first via and a third plating layer (the plated via hole; paragraph 21) disposed on an inside of the third via hole and coming in contact with the at least a part of the first plating layer (Fig. 1A, 1B), and disposed at the other end of the first via;
a first pad (120a) surrounding at least a part of an outside of the second via hole (321) and disposed vertically to the height direction of the interposer; and a second pad (120b) surrounding at least a part of an outside of the third via hole (331) and disposed vertically to the height direction of the interposer.
Marin does not explicitly disclose a first printed circuit board ; a second printed circuit board; and an interposer having one surface on which the first printed circuit board is disposed and the other surface on which the second printed circuit board is disposed.
Marin suggests an interposer (412, Fig. 4) having one surface on which the first printed circuit board (402) is disposed and the other surface on which a die (414) is disposed
Leopold teaches a first printed circuit board (442a, Fig. 4A); a second printed circuit board (442b); and an interposer (444) having one surface on which the first printed circuit board is disposed and the other surface on which the second printed circuit board is disposed.
It would have been obvious to one having skill in the art at the effective filing date of the invention to use an interposer in order to connect a circuit board to other electronic components such as another circuit board or a die or a device in order to complete an intended circuitry as designed.
Regarding claim 2, Marin discloses the claimed invention as set forth in claim 1. Marin further suggests the first via is formed so that a width of the first via (172, Fig. 1B) is larger than a width of one end of the second via (182a) and a width of one end of the third via (183a).
Regarding claim 6, Marin discloses the claimed invention as set forth in claim 1. Marin further suggests the first plating layer is disposed along an inner periphery of the first via hole with a thickness (170, Fig. 1B), and wherein the first via further includes an inner layer disposed in an inside direction of the first plating layer (the resin layer similar to 175; fig. 1A).
Regarding claim 7, Marin discloses the claimed invention as set forth in claim 1. Marin further suggests a copper foil (the via and pad are made of copper; paragraph 30; Fig. 3A), wherein at least a part of the copper foil is disposed on an outside of the first via hole (the top and bottom layer of the via 375 are layers of copper) at one end and the other end of the first via hole.
Claim(s) 3 - 4 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marin (US 20210014972), in view of Leopold (US 20210014972), in further view of Ganesan (US 12261124).
Regarding claim 3, Marin discloses the claimed invention as set forth in claim 1.
Marin does not explicitly disclose the second via comprises a pad seating area in which a part of the second via hole is bent in an inside direction of the second via hole in at least a part of the second via, and wherein the first pad is disposed in the pad seating area.
Ganesan suggests the second via comprises a pad seating area (the area for the pads of the via in the substrate 12, Fig. 1) in which a part of the second via hole is bent in an inside direction of the second via hole in at least a part of the second via (Fig. 1), and wherein the first pad is disposed in the pad seating area (the pad of the via in the substrate 12 is disposed on the bent space of the via; Fig. 1).
It would have been obvious to one having skill in the art at the effective filing date of the invention to modify the shape of the via for other component such as the pad in order to fit all component into the limited space of the circuit substrate.
Regarding claim 4, Marin discloses the claimed invention as set forth in claim 1.
Marin does not explicitly disclose the third via comprises a pad seating area in which a part of the third via hole is bent in an inside direction of the third via hole in at least a part of the third via, and wherein the second pad is disposed in the pad seating area.
Ganesan teaches the third via (the via in the substrate below substrate 72; Fig. 1) comprises a pad seating area (the area for the pad around the via below the substrate 72) in which a part of the third via hole is bent in an inside direction of the third via hole in at least a part of the third via, and wherein the second pad (the pad around the via in the substrate below the substrate 72) is disposed in the pad seating area.
It would have been obvious to one having skill in the art at the effective filing date of the invention to modify the shape of the via for other component such as the pad in order to fit all component into the limited space of the circuit substrate.
Claim(s) 10, 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Marin (US 20210014972), in view of Ganesan (US 12261124).
Regarding claim 10, Marin discloses the claimed invention as set forth in claim 8.
Marin does not explicitly disclose the second via comprises a pad seating area in which a part of the second via hole is bent in an inside direction of the second via hole in at least a part of the second via, and wherein the first pad is disposed in the pad seating area.
Ganesan suggests the second via comprises a pad seating area (the area for the pads of the via in the substrate 12, Fig. 1) in which a part of the second via hole is bent in an inside direction of the second via hole in at least a part of the second via (Fig. 1), and wherein the first pad is disposed in the pad seating area (the pad of the via in the substrate 12 is disposed on the bent space of the via; Fig. 1).
It would have been obvious to one having skill in the art at the effective filing date of the invention to modify the shape of the via for other component such as the pad in order to fit all component into the limited space of the circuit substrate.
Regarding claim 11, Marin discloses the claimed invention as set forth in claim 8.
Marin does not explicitly disclose the third via comprises a pad seating area in which a part of the third via hole is bent in an inside direction of the third via hole in at least a part of the third via, and wherein the second pad is disposed in the pad seating area.
Ganesan teaches the third via (the via in the substrate below substrate 72; Fig. 1) comprises a pad seating area (the area for the pad around the via below the substrate 72) in which a part of the third via hole is bent in an inside direction of the third via hole in at least a part of the third via, and wherein the second pad (the pad around the via in the substrate below the substrate 72) is disposed in the pad seating area.
It would have been obvious to one having skill in the art at the effective filing date of the invention to modify the shape of the via for other component such as the pad in order to fit all component into the limited space of the circuit substrate.
Allowable Subject Matter
Claim 15 is allowed.
Claims 5, 12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Reasons for Allowance
The following is an examiner’s statement of reasons for allowance:
Regarding claim 5, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 1, a combination of limitations that the first pad or the second pad comprises a pad opening, and wherein the pad opening includes a plurality of contact areas disposed along an outer periphery of the pad opening and bent in a direction toward an outside of the pad opening in at least a part of the pad opening. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 12, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 18 a combination of limitations that the first pad or the second pad comprises a pad opening, and wherein the pad opening includes a plurality of contact areas disposed along an outer periphery of the pad opening and bent in a direction toward an outside of the pad opening in at least a part of the pad opening. None of the reference art of record discloses or renders obvious such a combination.
Regarding claim 15, the prior art of record, taken alone or in combination, fails to teach or fairly suggest, in combining with other limitations recited in claim 15, a combination of limitations that disposing and laminating a third insulating layer (disposing layer 140b on 150) on one surface of the first insulating layer and a fourth insulating layer on the other surface of the second insulating layer; forming a pad and a circuit pattern on at least parts of the third insulating layer and the fourth insulating layer; disposing and laminating a fifth insulating layer on one surface of the third insulating layer and a sixth insulating layer on one surface of the fourth insulating layer; performing an oxide process on the fifth insulating layer and the sixth insulating layer; forming a second via hole penetrating the third insulating layer and the fifth insulating layer and a third via hole penetrating the fourth insulating layer and the sixth insulating layer by using a laser drilling method; forming a plating layer on insides of the second via hole and the third via hole; and forming a circuit pattern on at least parts of the fifth insulating layer and the sixth insulating layer, wherein the sixth insulating layer, the fourth insulating layer, the second insulating layer, the first insulating layer, the third insulating layer, and the fifth insulating layer are laminated in a height direction of the interposer. None of the reference art of record discloses or renders obvious such a combination.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Jomaa (US 20150296616) discloses a substrate having the via with different diameter; Fig. 15.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to BINH B TRAN whose telephone number is (571)272-9289. The examiner can normally be reached M-F 8:00 AM - 6:00 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy J Dole can be reached at 571-272-2229. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/BINH B TRAN/Primary Examiner, Art Unit 2848