DETAILED ACTION
This action is responsive to the following communications: the Amendment filed on February 23, 2026.
Claims 1-3, 5-15 and 17-20 are pending. Claims 1, 11 and 15 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings were received on February 23, 2026. These drawings are unacceptable.
All of the Figures filed on February 23, 2026 and June 17, 2024 are degraded, showing dotted lines and dotted lettering and numbering, which may indicate applicant submitted Figures that were in grayscale. The defect is most easily observable on Patent Center (and Docket Application Viewer, DAV) when increasing zoom to 300%. The lettering and features intended to be solid black, instead have regular patterns of white dots. See the following Examiner Markup Application’s Figure 3.
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The degraded quality, and the basis of the objection to the Drawings, is the Figures are not in solid black, but have features in shades of gray that caused pixelated. Here is a snapshot from recently filed PDF (not from the DRW Drawings of Record). The lettering for “Fig. 1” of Figure 1 is in color code #3C3C3B, which is a very dark gray.
The color codes #3C3C3B is 24-bit color codes expressed in hexadecimal format of #RRGGBB. A website that explains 24-bit color codes is here: RGB Color Codes Chart (https://www.rapidtables.com/web/color/RGB_Color.html). When viewing 24-bit images, what may appear on screen as black may not actually be black. Black is
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#000000. #3C3C3B is a very dark gray, but not black, which is causing the labeling and lines to appear in the Figures with a pattern of white dots (i.e., dithering).
Applicant is reminded that solid lines used in the Drawings must be uniformly thick, black, and solid and the words and labels in the Drawings must be plain and legible. MPEP 608.02(f)(V).
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-15 and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over Zainuddin et al. (US 20240290395), in view of Tian et al. (US 20240144996).
Regarding independent claim 1, Zainuddin et al. disclose an apparatus [Fig. 2: 200], comprising:
an array of memory cells [Fig. 2: 202, para. 41];
a controller [Fig. 2: 260] coupled to the array of memory cells [Fig. 2: 202, para. 37] and the controller is configured to:
apply a read voltage to a first word line in the array of memory cells during a read operation on the first word line [Fig. 6: step 612, applying a read reference voltage (Vcgr) to the selected word line which is the word line connected to the memory cells to be read, para. 107]; and
apply a bit line bias to a number of bit lines coupled to the first word line during the read operation on the first word line [Fig. 6: step 606, applying a lower voltage to the bit lines during the read operation on an open block, para. 105], wherein the bit line bias includes a bit line bias offset associated with performing the read operation on a partially programmed block [the magnitude of the voltage to apply to bit lines during the open block read depends on how may word lines are programmed in the open block. The more open the block (e.g., more unprogrammed word lines or higher percentage of unprogrammed word lines) the lower the bit line voltage, para. 105].
However, Zainuddin et al. are silent with respect to wherein the bit line bias offset is based upon a read level of the read voltage.
Tian et al. teach the bit line bias offset is based upon a read level of the read voltage [see Fig. 10, Tian et al. disclose reading target word line WLn at seven different reference voltages VrA-VrG and provides a table assigning bit line voltages to those read reference voltages, para. 110. See Fig. 13, Tian et al. provides an example: one set of bit line voltages is applied while WLn is at VrC and the bit line voltage are changed when WLn is raised toward VrF, para. 133-134].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Tian et al. to the teachings of Zainuddin et al. such that modifying bit line voltage control of Zainuddin et al. to select the magnitude of the bit line offset based upon to the read reference level as taught by Tian et al. to provide an appropriate sensing condition while maintaining Zainuddin et al.’s reduced bit line voltage and obtaining the predictable result of read level dependent bit line compensation.
Regarding claim 2, Zainuddin et al. in combination with Tian et al. teach the limitations with respect to claim 1.
Furthermore, Zainuddin et al. disclose the partially programmed block comprises a number of programmed word lines and a number of unprogrammed word lines [the memory controller 120 will track the last word line programmed in each tier in order to determine the degree of open-ness. The degree of open-ness may refer to either the percentage of word lines in the physical block that are unprogrammed or the number of word lines in the physical block that are unprogrammed, para. 86].
Regarding claim 3, Zainuddin et al. in combination with Tian et al. teach the limitations with respect to claim 1.
Furthermore, Zainuddin et al. disclose the controller is configured to apply a pass voltage to a number of word lines other than the first word line in the array of memory cells during the read operation [Fig. 6: step 610, applying a read pass voltage (Vread) to unselected word lines, para. 106].
Regarding claim 5, Zainuddin et al. in combination with Tian et al. teach the limitations with respect to claim 1.
Furthermore, Zainuddin et al. disclose the bit line bias offset associated with performing the read operation on the partially programmed block is based upon a word line group of the word line [the magnitude of the voltage to apply to bit lines during the open block read depends on how may word lines are programmed in the open block. The more open the block (e.g., more unprogrammed word lines or higher percentage of unprogrammed word lines) the lower the bit line voltage, para. 105].
Regarding claim 6, Zainuddin et al. in combination with Tian et al. teach the limitations with respect to claim 1.
Furthermore, Zainuddin et al. disclose the bit line bias offset is stored in a look up table (LUT) [the die may access a parameter table that specifies the bit line voltage for the open block read, para. 112].
Tian et al. also disclose the bit line bias offset is stored in a look up table (LUT) [see Fig. 10, a table 1000 that shows an embodiment of bit line voltages for different amount of bit line based compensation for neighbor memory cell interference, para. 110].
Regarding claim 7, Zainuddin et al. in combination with Tian et al. teach the limitations with respect to claim 6.
Furthermore, Zainuddin et al. disclose the LUT includes offset values for each of a number of word lines in the array of memory cells [the die may access a parameter table that specifies the bit line voltage for the open block read, para. 112. The magnitude of the voltage to apply to bit lines during the open block read depends on how may word lines are programmed in the open block. The more open the block (e.g., more unprogrammed word lines or higher percentage of unprogrammed word lines) the lower the bit line voltage, para. 105].
Regarding claim 8, Zainuddin et al. in combination with Tian et al. teach the limitations with respect to claim 6.
Furthermore, Tian et al. disclose the LUT includes offset values for each read level of a number read levels used during the read operation [see Fig. 10, Tian et al. disclose reading target word line WLn at seven different reference voltages VrA-VrG and provides a table assigning bit line voltages to those read reference voltages, para. 110].
Regarding claim 9, Zainuddin et al. in combination with Tian et al. teach the limitations with respect to claim 6.
Furthermore, Zainuddin et al. disclose the LUT is stored in the array of memory cells [the memory structure 202 may store the open block read parameters, including the voltages applied to bit lines, para. 37].
Regarding claim 10, Zainuddin et al. in combination with Tian et al. teach the limitations with respect to claim 6.
Furthermore, Zainuddin et al. disclose the LUT is stored in the controller [System control logic 260 includes storage 266 (e.g., RAM, registers, latches, etc.), which may be used to store parameters for operating the memory structure 202, including open block read parameters and bit line voltages, para. 37].
Regarding independent claim 11, Zainuddin et al. disclose an apparatus [Fig. 2: 200], comprising:
an array of memory cells [Fig. 2: 202, para. 41];
a controller [Fig. 2: 260] coupled to the array of memory cells [Fig. 2: 202, para. 37] and the controller is configured to:
receive a read command for data stored in a first word line of a partially programmed block [memory controller 120 sends a read command to the system control logic 260, indicates whether the read is to be an open block read or a closed block read and indicates the last word line that was programmed in the event that this is an open block read, para. 104];
apply a read voltage to a first word line in the array of memory cells in response to receiving the read command [Fig. 6: step 612, applying a read reference voltage (Vcgr) to the selected word line. The selected word line is the word line that is connected to the memory cells to be read, para. 107];
apply a pass voltage to a number of word lines other than the first word line in the array of memory cells in response to receiving the read command [Fig. 6: step 610, applying a read pass voltage (Vread) to unselected word lines, para. 106]; and
apply a bit line bias to a number of bit lines coupled to the first word line in response to receiving the read command [Fig. 6: step 606, applying a lower voltage to the bit lines during the read operation on an open block, para. 105], wherein the bit line bias includes a bit line bias offset associated with performing the read operation on a partially programmed block [the magnitude of the voltage to apply to bit lines during the open block read depends on how may word lines are programmed in the open block. The more open the block (e.g., more unprogrammed word lines or higher percentage of unprogrammed word lines) the lower the bit line voltage, para. 105].
However, Zainuddin et al. are silent with respect to wherein the bit line bias offset is based upon a read level of the read voltage.
Tian et al. teach the bit line bias offset is based upon a read level of the read voltage [see Fig. 10, Tian et al. disclose reading target word line WLn at seven different reference voltages VrA-VrG and provides a table assigning bit line voltages to those read reference voltages, para. 110. See Fig. 13, Tian et al. provides an example: one set of bit line voltages is applied while WLn is at VrC and the bit line voltage are changed when WLn is raised toward VrF, para. 133-134].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Tian et al. to the teachings of Zainuddin et al. such that modifying bit line voltage control of Zainuddin et al. to select the magnitude of the bit line offset based upon to the read reference level as taught by Tian et al. to provide an appropriate sensing condition while maintaining Zainuddin et al.’s reduced bit line voltage and obtaining the predictable result of read level dependent bit line compensation.
Regarding claim 12, Zainuddin et al. in combination with Tian et al. teach the limitations with respect to claim 11.
Furthermore, Tian et al. disclose the bit line bias offset associated with reading the data on the first word line is based upon the read level of the read voltage being applied to the first word line [see Fig. 10, Tian et al. disclose reading target word line WLn at seven different reference voltages VrA-VrG and provides a table assigning bit line voltages to those read reference voltages, para. 110. See Fig. 13, Tian et al. provides an example: one set of bit line voltages is applied while WLn is at VrC and the bit line voltage are changed when WLn is raised toward VrF, para. 133-134].
Regarding claim 13, Zainuddin et al. in combination with Tian et al. teach the limitations with respect to claim 11.
Furthermore, Zainuddin et al. disclose the bit line bias offset associated with reading the data on the first word line is based upon a word line group of the word line [the magnitude of the voltage to apply to bit lines during the open block read depends on how may word lines are programmed in the open block. The more open the block (e.g., more unprogrammed word lines or higher percentage of unprogrammed word lines) the lower the bit line voltage, para. 105].
Regarding claim 14, Zainuddin et al. in combination with Tian et al. teach the limitations with respect to claim 11.
Furthermore, Zainuddin et al. disclose the bit line bias offset is stored in a look up table (LUT) [the die may access a parameter table that specifies the bit line voltage for the open block read, para. 112].
Tian et al. also disclose the bit line bias offset is stored in a look up table (LUT) [see Fig. 10, a table 1000 that shows an embodiment of bit line voltages for different amount of bit line based compensation for neighbor memory cell interference, para. 110].
Regarding independent claim 15, Zainuddin et al. disclose a method [Fig. 6], comprising:
performing a read operation on a word line in a memory array [Fig. 6: step 602-604, para. 102-104]
wherein performing the read operation includes:
applying a read voltage to a first word line in the array of memory cells during a read operation on the first word line [Fig. 6: step 612, applying a read reference voltage (Vcgr) to the selected word line. The selected word line is the word line that is connected to the memory cells to be read, para. 107]; and
applying a bit line bias to a number of bit lines coupled to the first word line during the read operation on the first word line [Fig. 6: step 606, applying a lower voltage to the bit lines during the read operation on an open block, para. 105], wherein the bit line bias includes a bit line bias offset associated with performing the read operation on a partially programmed block [the magnitude of the voltage to apply to bit lines during the open block read depends on how may word lines are programmed in the open block. The more open the block (e.g., more unprogrammed word lines or higher percentage of unprogrammed word lines) the lower the bit line voltage, para. 105].
However, Zainuddin et al. are silent with respect to wherein the bit line bias offset is based upon a read level of the read voltage.
Tian et al. teach the bit line bias offset is based upon a read level of the read voltage [see Fig. 10, Tian et al. disclose reading target word line WLn at seven different reference voltages VrA-VrG and provides a table assigning bit line voltages to those read reference voltages, para. 110. See Fig. 13, Tian et al. provides an example: one set of bit line voltages is applied while WLn is at VrC and the bit line voltage are changed when WLn is raised toward VrF, para. 133-134].
It would have been obvious to a person having ordinary skill in the art before the effective filling date of the claimed invention to apply the teachings of Tian et al. to the teachings of Zainuddin et al. such that modifying bit line voltage control of Zainuddin et al. to select the magnitude of the bit line offset based upon to the read reference level as taught by Tian et al. to provide an appropriate sensing condition while maintaining Zainuddin et al.’s reduced bit line voltage and obtaining the predictable result of read level dependent bit line compensation.
Regarding claim 17, Zainuddin et al. in combination with Tian et al. teach the limitations with respect to claim 15.
Furthermore, Zainuddin et al. disclose applying the bit line bias offset associated with performing the read operation on the partially programmed block is based upon a word line group of the first word line [the magnitude of the voltage to apply to bit lines during the open block read depends on how may word lines are programmed in the open block. The more open the block (e.g., more unprogrammed word lines or higher percentage of unprogrammed word lines) the lower the bit line voltage, para. 105].
Regarding claim 18, Zainuddin et al. teach the limitations with respect to claim 15.
Furthermore, Zainuddin et al. disclose including reading a bit line bias offset value from a look up table (LUT) to apply to the bit line during the read operation [Fig. 2A: 261, the memory structure 202 stores the open block read parameters 261, which may be loaded into storage 266 when the die is powered on. Such open block read parameters 261 includes one or more voltages to apply to bit lines during an open block read, para. 37].
Regarding claim 19, Zainuddin et al. in combination with Tian et al. teach the limitations with respect to claim 15.
Furthermore, Zainuddin et al. disclose further including storing a number of bit line bias offset values in the LUT [the die may access a parameter table that specifies the bit line voltage for the open block read, para. 112].
Tian et al. also disclose further including storing a number of bit line bias offset values in the LUT [see Fig. 10, a table 1000 that shows an embodiment of bit line voltages for different amount of bit line based compensation for neighbor memory cell interference, para. 110].
Regarding claim 20, Zainuddin et al. teach the limitations with respect to claim 18.
Furthermore, Zainuddin et al. disclose further including storing the number of bit line bias offset values in the LUT based upon a number of word line groups [the magnitude of the voltage to apply to bit lines during the open block read depends on how may word lines are programmed in the open block. The more open the block (e.g., more unprogrammed word lines or higher percentage of unprogrammed word lines) the lower the bit line voltage, para. 105].
Tian et al. teach storing the number of bit line bias offset values in the LUT based upon a number read levels in the read operation [see Fig. 10, Tian et al. disclose reading target word line WLn at seven different reference voltages VrA-VrG and provides a table assigning bit line voltages to those read reference voltages, para. 110. See Fig. 13, Tian et al. provides an example: one set of bit line voltages is applied while WLn is at VrC and the bit line voltage are changed when WLn is raised toward VrF, para. 133-134].
Response to Arguments
Applicant’s arguments with respect to claims 1-3, 5-15 and 17-20 (esp. independent claims 1, 11 and 15) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DUY H LUONG whose telephone number is (571)270-5088. The examiner can normally be reached Mon-Fri. 9am-6pm.
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/DUY H LUONG/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825
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