Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Detailed Action
2. This office action is in response to the filing with the office dated 06/17/2024.
Information Disclosure Statement
3. The information disclosure statements (IDS) submitted on 06/21/2024 and 12/19/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Application Priority
4. This application claims priority to a U.S. provisional application 63/567874 filed on 03/20/2024. However upon a careful examination of the contents of the provisional application (specification, drawings and claim) and comparing it with the non-provisional application (specification, drawings and claim), it is determined that the claims filed on 06/17/2024 do not have support in the provisional application. Hence the applicant’s claim of priority to the provisional filing date is denied. Hence this application will have a priority date of the Non-provisional application filing date (06/17/2024).
The later-filed application must be an application for a patent for an invention which is also disclosed in the prior application (the parent or original nonprovisional application or provisional application). The disclosure of the invention in the parent application and in the later-filed application must be sufficient to comply with the requirements of 35 U.S.C. 112(a) or the first paragraph of pre-AIA 35 U.S.C. 112, except for the best mode requirement. See Transco Products, Inc. v. Performance Contracting, Inc., 38 F.3d 551, 32 USPQ2d 1077 (Fed. Cir. 1994).
The disclosure of the prior-filed application, Application No. 63/567874 fails to provide adequate support or enablement in the manner provided by 35 U.S.C. 112(a) or pre-AIA 35 U.S.C. 112, first paragraph for one or more claims of this application. Voltage transfer curve in claims 1, 3, 4, 9, 11-13 and 16 is not taught in the provisional application.
This application repeats a substantial portion of prior Application No. 63/567874, filed 03/20/2024 and adds disclosure not presented in the prior application. Because this application names the inventor or at least one joint inventor named in the prior application, it may constitute a continuation-in-part of the prior application. Should applicant desire to claim the benefit of the filing date of the prior application, attention is directed to 35 U.S.C. 120, 37 CFR 1.78, and MPEP § 211 et seq. The presentation of a benefit claim may result in an additional fee under 37 CFR 1.17(w)(1) or (2) being required, if the earliest filing date for which benefit is claimed under 35 U.S.C. 120, 121, 365(c), or 386(c) and 1.78(d) in the application is more than six years before the actual filing date of the application.
Claim Rejections – 35 U.S.C. 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
5. Claim 1, 8, and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 8, and 15 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being incomplete for omitting essential steps, such omission amounting to a gap between the steps. See MPEP § 2172.01. The omitted steps are:
Claim 1 recites a crystal driver. it is not clear what is meant by a crystal driver, whether it is driver circuit for a crystal oscillator or something else like a particular circuit configuration. It is also not clear how a gain margin of the crystal driver can be determined on a single voltage measurement. According to paragraph [0042] of the instant specification, at least two different currents are required to measure the gain margin.
It is also not clear how by applying a current bias to the input of the driver would result in a voltage value within a voltage transfer curve at the output of the driver. Appropriate correction to the claim language is required to bring clarity to the recitation.
Specification objection
6. Claims 9 and 13 and paragraphs [0022],[0047],[0051],[0052],[0054],[0056],[0057]) of the specification recite “and an driver output”. Appropriate grammar correction is required.
Claim Rejections – 35 U.S.C. 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
7. Claims 1-3, 6-11 are rejected under 35 U.S.C. 102 (a) (1) as being anticipated by Oomori (US 2022/0173698 A1) et al.
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Regarding independent claim 1, Oomori (US 2022/0173698 A1) et al teaches, method comprising: providing a device (figure 1, crystal oscillator circuit) comprising: a crystal driver to operate according to a voltage transfer curve and having a driver input and a driver output (figure2, paragraph [0031]); and a first current reference to provide a first current bias to the driver input to produce a first voltage at the driver output within a linear region of the voltage transfer curve of the crystal driver (figure 3, paragraph [0051]-[0056]); forcing the first current bias from the first current bias on the driver input (paragraphs [0032]-[0035]); measuring the first voltage on the driver output; and determining a gain margin of the crystal driver based on the measured first voltage on the driver output (paragraphs [0041]-[0046] [0041] FIG. 3 is a circuit diagram in which the configuration of FIG. 1 is replaced by an equivalent circuit. The crystal resonator XTAL is replaced by an inductance Le and an effective resistor Re. The crystal oscillator circuit 100 is replaced by a load capacitance CL and a negative resistor −RL.[0042] The load capacitance CL and the negative resistance −RL are expressed by the next formulae (1) and (2), respectively.
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[0043] Note that a conductance of each inverter constituting the crystal oscillator circuit 100 is expressed by the next formula (3) using an input voltage Vin and an output current Iout.
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[0044] An oscillation condition in the configuration is expressed by the next formula (4).
[00003]-RL≥Re (4)
[0045] That is, when the above-described condition is met, the effective resistance Re of the crystal resonator XTAL is canceled by the negative resistance −RL, and impedance loss of the crystal oscillator circuit 100 is eliminated. This causes an LC oscillation by the inductance Le and the load capacitance CL, thus ensuring oscillation. [0046] For stable oscillation, the negative resistance −RL needs to be smaller than 0 Ω, and an absolute value of the negative resistance −RL needs to be a constant one time or more of the effective resistance Re. When an oscillation margin indicative of a margin from an oscillation state to oscillation stop is denoted as n, the oscillation margin n is expressed by the next formula (5).
[00004]n=.Math.-RL.Math./Re(5)
[0047] Generally, the oscillation margin n is preferably three times or more of the effective resistance Re in the commercial crystal oscillator, and is preferably five times or more of the effective resistance Re in an on-board crystal oscillator. [0065] With the above-described formula (2), decreasing the oscillation capacitances Cg and Cd increases the negative resistance −RL, and increasing the oscillation capacitances Cg and Cd reduces the negative resistance −RL. Similarly, increasing the conductance gm of the inverter INV constituting the oscillation amplifier also increases the negative resistance—RL, and reducing the conductance gm of the inverter INV also reduces the negative resistance −RL. With the above-described formula (1), the oscillation capacitances Cg and Cd are determined by the load capacitance CL of the crystal resonator XTAL used. With the crystal oscillator circuit of the first comparative example, by adjusting the circuit constants, the negative resistance −RL is adjusted so as to be a desired oscillation margin according to the crystal resonator XTAL used.
Please see the 35 U.S.C. 112 rejection above. It is not clear how the gain margin can be determined from one measurement.
Claim 1 recites a crystal driver. it is not clear what is meant by a crystal driver, whether it is driver circuit for a crystal oscillator or something else like a particular circuit configuration. It is also not clear how a gain margin of the crystal driver can be determined on a single voltage measurement. According to paragraph [0042] of the instant specification, at least two different currents are required to measure the gain margin.
It is also not clear how by applying a current bias to the input of the driver would result in a voltage value within a voltage transfer curve at the output of the driver. Appropriate correction to the claim language is required to bring clarity to the recitation.
Regarding dependent claim 2, Oomori (US 2022/0173698 A1) et al teaches, the method as in claim 1.
Oomori (US 2022/0173698 A1) et al further teaches, comprising: shorting the driver output to the driver input while forcing the first current bias from the first internal current reference on the driver input (paragraphs [0046], [0047], [0065]); measuring a second voltage on the driver output; and determining a gain margin of the crystal driver based on the measured first and second voltages on the driver output (paragraphs [0046], [0047], [0065]).
Regarding dependent claim 3, Oomori (US 2022/0173698 A1) et al teaches, the method as in claim 1.
Oomori (US 2022/0173698 A1) et al further teaches, wherein the provided the device comprises: a second current reference to provide a second current bias to the driver input to produce a second voltage at the driver output within a linear region of the voltage transfer curve of the crystal driver (paragraphs [0046], [0047], [0051]-[0056], [0065]); and an input switch to switch between the first current bias and the second current bias; the method comprising: forcing the second current bias on the driver input; measuring a second voltage on the driver output (paragraphs [0046], [0047], [0051]-[0056], [0065]); and determining the gain margin of the crystal driver based on the measured first and second voltages on the driver output (paragraphs [0046], [0047], [0051]-[0056], [0065]).
Regarding dependent claim 6, Oomori (US 2022/0173698 A1) et al teaches, the method as in claim 1.
Oomori (US 2022/0173698 A1) et al further teaches, comprising measuring a second voltage on the driver output, wherein determining the gain margin of the crystal driver is based on the measured first and second voltages on the driver output (paragraphs [0046], [0047], [0065]).
Regarding dependent claim 7, Oomori (US 2022/0173698 A1) et al teaches, the method as in claim 1.
Oomori (US 2022/0173698 A1) et al further teaches, comprising forcing a zero bias current on the driver input; measuring a second voltage on the driver output; and determining a gain margin of the crystal driver by dividing a difference between the first current bias and zero current bias by a difference between the first and second voltages (equation 3, paragraphs [0043], [0046], [0047], [0065]).
Regarding dependent claim 8, Oomori (US 2022/0173698 A1) et al teaches, the method as in claim 1.
Oomori (US 2022/0173698 A1) et al further teaches, comprising forcing a second current bias on the driver input; measuring a second voltage on the driver output; and determining the gain margin of the crystal driver by dividing the difference between the first and second current biases by the difference between the first and second voltages (paragraphs [0043] equation 3, [0046], [0047], [0065]).
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Regarding independent claim 9, Oomori (US 2022/0173698 A1) et al teaches, A device (figure 1, crystal oscillator circuit) comprising: a crystal driver to operate according to a voltage transfer curve and having an driver input, and an driver output (figure2, paragraph [0031]); and a first current reference to provide a first current bias to the driver input to produce a first voltage at the driver output within a linear region of the voltage transfer curve of the crystal driver (figure 3, paragraphs [0046], [0047], [0051]-[0056]).
Regarding dependent claim 10, Oomori (US 2022/0173698 A1) et al teaches the device as in claim 9.
Oomori (US 2022/0173698 A1) et al teaches, comprising a feedback switch to short the driver output to the driver input to provide a zero current bias to the driver input when the feedback switch is closed (figure 2, paragraphs [0048]-[0056]).
Regarding dependent claim 11, Oomori (US 2022/0173698 A1) et al teaches the device as in claim 9.
Oomori (US 2022/0173698 A1) et al teaches, comprising: a second current reference to provide a second current bias to the driver input to produce a second voltage at the driver output within a linear region of the voltage transfer curve of the crystal driver (paragraphs [0046], [0047], [0065]); and an input switch to switch between the first current bias and the second current bias (paragraphs [0046], [0047], [0065]).
Claim Rejections – 35 U.S.C. 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
8. Claims 4, 5, 12-20 are rejected under 35 U.S.C. 103 as being unpatentable over Oomori (US 2022/0173698 A1) et al and in view of Jefremow et al (US 2022/0131499 A1).
Regarding dependent claim 4, Oomori (US 2022/0173698 A1) et al teaches, the method as in claim 1.
Oomori et al does not explicitly teach a current mirror but further teaches, [0048] With reference to FIG. 2 again, the crystal oscillator circuit 100 of this embodiment is, as described above, constituted of the oscillation amplifier including the inverters of three stages, the first feedback resistor Rf1, and the oscillation capacitances (Cg/Cd).
Oomari et al is silent about, a programable current mirror to provide the first current bias from the first current reference to the driver input and to provide a second current bias from the first current reference to the driver input, wherein the first and second current biases are to produce a first voltage and a second voltage at the driver output, respectively, that are within the linear region of the voltage transfer curve of the crystal driver; the method comprising: forcing the second current bias on the driver input; measuring the second voltage on the driver output; and determining the gain margin of the crystal driver based on the measured first and second voltages on the driver output.
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Jefremow et al (US 2022/0131499 A1) teaches, (figures 5A-5C, paragraphs [0035]-[0039], [0040] FIG. 6A illustrates an exemplary oscillator system 600 that supports negative resistance margin testing in which resistance control circuitry includes a PWM signal generator. Amplifier circuitry 640 includes three gain stages A1, A2, and A3. The output stage A3 is a PWM controlled gain stage that serves as variable resistance circuitry 650. In other examples a different amplifier stage may serve as variable resistance circuitry 650. PWM circuitry 636 generates a PWM signal that
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has a variable duty cycle to control the gain of the amplifier stage 650. In one example, the PWM circuitry 636 includes a generic timer module (GTM) which is a common component found in many automotive microcontrollers.[0042] Detection circuitry 632 (e.g., PLL or voltage detector),
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which may be implemented on the oscillator circuit 610 or external to the oscillator circuit, monitors the oscillator signal and generates a quality indicator that indicates a satisfactory oscillator signal or an unsatisfactory oscillator signal. The control and monitor circuitry 634 monitors the quality indicator to determine whether the oscillator signal is satisfactory. The control and monitor circuitry 634 determines the negative resistance margin based on the duty cycle of the resistance control signal at the time the quality indicator indicates an unsatisfactory oscillator signal. The control and monitor circuitry 634 outputs a margin signal that communicates the determined negative resistance margin. [0043] FIG. 6B illustrates an exemplary PWM controlled amplifier driver stage 650. The PWM resistance control signal, which may be generated by a software-controlled GTM, is first processed by a low pass filter (LPF) and biasing circuitry 638 and injected into the amplifier driver stage 650. FIG. 6C illustrates the LPF and biasing circuitry 638 in more detail. The LPF and biasing circuitry 638 includes a CMOS switch M1 which is used as a variable resistor in series with the amplifier circuitry 640 (note that the footprint capacitances C.sub.F1 and C.sub.F2 are associated with the microcontroller). The LPF and biasing circuitry 638 includes a replica of oscillator output voltage A′, second CMOS switch M2 (which is a replica of M1), Isource (which is a constant current from a current mirror), and Isink (which is the current from the current mirror that can be switched on or off by the timer circuit). It can be seen that the gate of M1 will be one Vth higher than the oscillator output voltage when Isink is off).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Oomori et al by providing a margin testing circuit which includes a voltage detector as taught by Jefremow et al (paragraphs [0035-[0039]).
One of the ordinary skill in the art would have been motivated to make such a modification so that the voltage detector sets an amplitude flag when the oscillator signal's amplitude is higher than a predefined threshold value, which is controlled by the reference value VREF. Thus, in this example, the voltage detector 532 is the detection circuitry and the amplitude flag is the quality indicator. The control and monitor circuitry 534 monitors the amplitude flag to determine whether the oscillator signal is satisfactory. The control and monitor circuitry 534 determines the negative resistance margin based on the value of the resistance control signal at the time the amplitude flag is reset, as taught by Jefremow et al (paragraph [0037], [0042]).
Regarding dependent claim 5, Oomori (US 2022/0173698 A1) et al teaches, the method as in claim 1.
Oomori (US 2022/0173698 A1) et al is silent, wherein measuring the first voltage on the driver output comprises measuring with an external voltage instrument having an accuracy of +/- 100mV.
However commercial oscilloscopes (Tektronix 7 series) or Keithley SMU (source measurement units 24XX series) are capable of measuring voltages of the order of microvolts and nanovolts.
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Oomari et al by providing an external voltage instrument having high accuracy such as a Tektronix or a voltage measuring instrument like an SMU or a Keithley nanovoltmeter.
One of the ordinary skill in the art would have been motivated to make such a modification so that an accurate voltage measurement can be performed.
Regarding dependent claim 12, Oomori (US 2022/0173698 A1) et al teaches the device as in claim 9.
Oomori (US 2022/0173698 A1) et al teaches providing first and second bias (paragraphs [0046][0047], [0065]).
Oomori (US 2022/0173698 A1) et al is silent about, a programable current mirror to provide the first current bias from the first current reference to the driver input and to provide a second current bias from the first current reference to the driver input, wherein the first and second current biases are to produce the first voltage and a second voltage at the driver output, respectively, that are within a linear region of the voltage transfer curve of the crystal driver.
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Jefremow et al (US 2022/0131499 A1) teaches, (figures 5A-5C, paragraphs [0035]-[0039], [0040] FIG. 6A illustrates an exemplary oscillator system 600 that supports negative resistance margin testing in which resistance control circuitry includes a PWM signal generator. Amplifier circuitry 640 includes three gain stages A1, A2, and A3. The output stage A3 is a PWM controlled gain stage that serves as variable resistance circuitry 650. In other examples a different amplifier stage may serve as variable resistance circuitry 650. PWM circuitry 636 generates a PWM signal that has a variable duty cycle to control the gain of the amplifier stage 650. In one example, the PWM circuitry 636 includes a generic timer module (GTM) which is a common component found in many automotive microcontrollers.[0042] Detection circuitry 632 (e.g., PLL or voltage detector), which may be implemented on the oscillator circuit 610 or external to the oscillator circuit, monitors the oscillator signal and generates a quality indicator that indicates a satisfactory oscillator signal or an unsatisfactory oscillator signal. The control and monitor
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circuitry 634 monitors the quality indicator to determine whether the oscillator signal is satisfactory. The control and monitor circuitry 634 determines the negative resistance margin based on the duty cycle of the resistance control signal at the time the quality indicator indicates an unsatisfactory oscillator signal. The control and monitor circuitry 634 outputs a margin signal that communicates the determined negative resistance margin.[0043] FIG. 6B illustrates an exemplary PWM controlled amplifier driver stage 650. The PWM resistance control signal, which may be generated by a software-controlled GTM, is first processed by a low pass filter (LPF) and biasing circuitry 638 and injected into the amplifier driver stage 650. FIG. 6C illustrates the LPF and biasing circuitry 638 in more detail. The LPF and biasing circuitry 638 includes a CMOS switch M1 which is used as a variable resistor in series with the amplifier circuitry 640 (note that the footprint capacitances C.sub.F1 and C.sub.F2 are associated with the microcontroller). The LPF and biasing circuitry 638 includes a replica of oscillator output voltage A′, second CMOS switch M2 (which is a replica of M1), Isource (which is a constant current from a current mirror), and Isink (which is the current from the current mirror that can be switched on or off by the timer circuit). It can be seen that the gate of M1 will be one Vth higher than the oscillator output voltage when Isink is off).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Oomori et al by providing a margin testing circuit which includes a voltage detector as taught by Jefremow et al (paragraphs [0035-[0039]).
One of the ordinary skill in the art would have been motivated to make such a modification so that the voltage detector sets an amplitude flag when the oscillator signal's amplitude is higher than a predefined threshold value, which is controlled by the reference value VREF. Thus, in this example, the voltage detector 532 is the detection circuitry and the amplitude flag is the quality indicator. The control and monitor circuitry 534 monitors the amplitude flag to determine whether the oscillator signal is satisfactory. The control and monitor circuitry 534 determines the negative resistance margin based on the value of the resistance control signal at the time the amplitude flag is reset, as taught by Jefremow et al (paragraph [0037]).
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Regarding independent claim 13, Oomori (US 20220173698 A1) et al teaches a system comprising: a device (figure 1, crystal oscillator circuit) comprising: a crystal driver to operate according to a voltage transfer curve and having an driver input, and an driver output (figure2, paragraph [0031]); and a first current reference to provide a first current bias to the
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driver input to produce a first voltage at the driver output within a linear region of the voltage transfer curve of the crystal driver (figure 3, paragraph [0051]-[0056]); and a voltage measuring instrument to measure the first voltage on the driver output when the first current bias is forced on the driver input (paragraphs [0046], [0047], [0065]).
Oomori et al does not explicitly teach a voltage measuring instrument but teaches, input voltage Vin and output current Iout in paragraph [0043]).
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Jefremow et al (US 2022/0131499 A1) teaches, (figures 5A-5C, paragraphs [0035]-[0039], [0040] FIG. 6A illustrates an exemplary oscillator system 600 that supports negative resistance margin testing in which resistance control circuitry includes a PWM signal generator. Amplifier circuitry 640 includes three gain stages A1, A2, and A3. The output stage A3 is a PWM controlled gain stage that serves as variable resistance circuitry 650. In other examples a different amplifier stage may serve as variable resistance circuitry 650. PWM circuitry 636 generates a PWM signal that has a variable duty cycle to control the gain of the amplifier stage 650. In one example, the PWM circuitry 636 includes a generic timer module (GTM) which is a common component found in many automotive microcontrollers. [0042] Detection circuitry 632 (e.g., PLL or voltage detector), which may be implemented on the oscillator circuit 610 or external to the oscillator circuit, monitors the oscillator signal and generates a quality indicator that indicates a satisfactory oscillator signal or an unsatisfactory oscillator signal. The control and monitor circuitry 634 monitors the quality indicator to determine whether the oscillator signal is satisfactory. The control and monitor circuitry 634 determines the negative resistance margin based on the duty cycle of the resistance control signal at the time the quality indicator indicates an unsatisfactory oscillator signal. The control and monitor circuitry 634 outputs a margin signal that communicates the determined negative resistance margin. [0043] FIG. 6B illustrates an exemplary PWM controlled amplifier driver stage 650. The PWM resistance control signal, which may be generated by a software-controlled GTM, is first processed by a low pass filter (LPF) and biasing circuitry 638 and injected into the amplifier driver stage 650. FIG. 6C illustrates the LPF and biasing circuitry 638 in more detail. The LPF and biasing circuitry 638 includes a CMOS switch M1 which is used as a variable resistor in series with the amplifier circuitry 640 (note that the footprint capacitances C.sub.F1 and C.sub.F2 are associated with the microcontroller). The LPF and biasing circuitry 638 includes a replica of oscillator output voltage A′, second CMOS switch M2 (which is a replica of M1), Isource (which is a constant current from a current mirror), and Isink (which is the current from the current mirror that can be switched on or off by the timer circuit). It can be seen that the gate of M1 will be one Vth higher than the oscillator output voltage when Isink is off).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Oomori et al by providing a margin testing circuit which includes a voltage detector as taught by Jefremow et al (paragraphs [0035-[0039]).
One of the ordinary skill in the art would have been motivated to make such a modification so that the voltage detector sets an amplitude flag when the oscillator signal's amplitude is higher than a predefined threshold value, which is controlled by the reference value VREF. Thus, in this example, the voltage detector 532 is the detection circuitry and the amplitude flag is the quality indicator. The control and monitor circuitry 534 monitors the amplitude flag to determine whether the oscillator signal is satisfactory. The control and monitor circuitry 534 determines the negative resistance margin based on the value of the resistance control signal at the time the amplitude flag is reset, as taught by Jefremow et al (paragraph [0037]).
Regarding dependent claim 14, Oomori (US 2022/0173698 A1) et al and Jefremow et al (US 2022/0131499 A1) teach the system as in claim 13.
Oomori (US 2022/0173698 A1) et al further teaches wherein the device comprises a feedback switch to short the driver output to the driver input to provide a zero current bias to the driver input when the feedback switch is closed to produce a second voltage on the driver output (figure2, paragraphs [0046]-[0048], [0051]-[0056]).
Regarding dependent claim 15, Oomori (US 2022/0173698 A1) et al and Jefremow et al (US 2022/0131499 A1) teach the system as in claim 14.
Oomori (US 2022/0173698 A1) et al further teaches, wherein the voltage measuring instrument is to measure the second voltage at the driver output when the zero current bias is provided on the driver input (Paragraph [0046][0047]).
Oomori et al does not explicitly teach a voltage measuring instrument but teaches, input voltage Vin and output current Iout in paragraph [0043]).
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Jefremow et al (US 2022/0131499 A1) teaches, (figures 5A-5C, paragraphs [0035]-[0039], [0040] FIG. 6A illustrates an exemplary oscillator system 600 that supports negative resistance margin testing in which resistance control circuitry includes a PWM signal generator. Amplifier circuitry 640 includes three gain stages A1, A2, and A3. The output stage A3 is a PWM controlled gain stage that serves as variable resistance circuitry 650. In other examples a different amplifier stage may serve as variable resistance circuitry 650. PWM circuitry 636 generates a PWM signal that has a variable duty cycle to control the gain of the amplifier stage 650. In one example, the PWM circuitry 636 includes a generic timer module (GTM) which is a common component found in many automotive microcontrollers. [0042] Detection circuitry 632 (e.g., PLL or voltage detector), which may be implemented on the oscillator circuit 610 or external to the oscillator circuit, monitors the oscillator signal and generates a quality indicator that indicates a satisfactory oscillator signal or an unsatisfactory oscillator signal. The control and monitor circuitry 634 monitors the quality indicator to determine whether the oscillator signal is satisfactory. The control and monitor circuitry 634 determines the negative resistance margin based on the duty cycle of the resistance control signal at the time the quality indicator indicates an unsatisfactory oscillator signal. The control and monitor circuitry 634 outputs a margin signal that communicates the determined negative resistance margin. [0043] FIG. 6B illustrates an exemplary PWM controlled amplifier driver stage 650. The PWM resistance control signal, which may be generated by a software-controlled GTM, is first processed by a low pass filter (LPF) and biasing circuitry 638 and injected into the amplifier driver stage 650. FIG. 6C illustrates the LPF and biasing circuitry 638 in more detail. The LPF and biasing circuitry 638 includes a CMOS switch M1 which is used as a variable resistor in series with the amplifier circuitry 640 (note that the footprint capacitances C.sub.F1 and C.sub.F2 are associated with the microcontroller). The LPF and biasing circuitry 638 includes a replica of oscillator output voltage A′, second CMOS switch M2 (which is a replica of M1), Isource (which is a constant current from a current mirror), and Isink (which is the current from the current mirror that can be switched on or off by the timer circuit). It can be seen that the gate of M1 will be one Vth higher than the oscillator output voltage when Isink is off).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Oomori et al by providing a margin testing circuit which includes a voltage detector as taught by Jefremow et al (paragraphs [0035-[0039]).
One of the ordinary skill in the art would have been motivated to make such a modification so that the voltage detector sets an amplitude flag when the oscillator signal's amplitude is higher than a predefined threshold value, which is controlled by the reference value VREF. Thus, in this example, the voltage detector 532 is the detection circuitry and the amplitude flag is the quality indicator. The control and monitor circuitry 534 monitors the amplitude flag to determine whether the oscillator signal is satisfactory. The control and monitor circuitry 534 determines the negative resistance margin based on the value of the resistance control signal at the time the amplitude flag is reset, as taught by Jefremow et al (paragraph [0037]).
Regarding dependent claim 16, Oomori (US 2022/0173698 A1) et al and Jefremow et al (US 2022/0131499 A1) the system as in claim 13.
Oomori (US 2022/0173698 A1) et al further teaches,, wherein the device comprises: a second current reference to provide a second current bias to the driver input to produce a second voltage at the driver output within a linear region of the voltage transfer curve of the crystal driver (paragraphs [0046][0047], [0065]); and an input switch to switch between the first current bias and the second current bias (paragraphs [0046][0047], [0065]).
Regarding dependent claim 17, Oomori (US 2022/0173698 A1) et al and Jefremow et al (US 2022/0131499 A1) the system as in claim 16.
Oomori (US 2022/0173698 A1) et al further teaches, wherein the voltage measuring instrument is to measure the second voltage at the driver output when the second current bias is provided to the driver input (paragraphs [0046][0047], [0065]).
Oomori et al does not explicitly teach a voltage measuring instrument but teaches, input voltage Vin and output current Iout in paragraph [0043]).
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Jefremow et al (US 2022/0131499 A1) teaches, (figures 5A-5C, paragraphs [0035]-[0039], [0040] FIG. 6A illustrates an exemplary oscillator system 600 that supports negative resistance margin testing in which resistance control circuitry includes a PWM signal generator. Amplifier circuitry 640 includes three gain stages A1, A2, and A3. The output stage A3 is a PWM controlled gain stage that serves as variable resistance circuitry 650. In other examples a different amplifier stage may serve as variable resistance circuitry 650. PWM circuitry 636 generates a PWM signal that has a variable duty cycle to control the gain of the amplifier stage 650. In one example, the PWM circuitry 636 includes a generic timer module (GTM) which is a common component found in many automotive microcontrollers. [0042] Detection circuitry 632 (e.g., PLL or voltage detector), which may be implemented on the oscillator circuit 610 or external to the oscillator circuit, monitors the oscillator signal and generates a quality indicator that indicates a satisfactory oscillator signal or an unsatisfactory oscillator signal. The control and monitor circuitry 634 monitors the quality indicator to determine whether the oscillator signal is satisfactory. The control and monitor circuitry 634 determines the negative resistance margin based on the duty cycle of the resistance control signal at the time the quality indicator indicates an unsatisfactory oscillator signal. The control and monitor circuitry 634 outputs a margin signal that communicates the determined negative resistance margin. [0043] FIG. 6B illustrates an exemplary PWM controlled amplifier driver stage 650. The PWM resistance control signal, which may be generated by a software-controlled GTM, is first processed by a low pass filter (LPF) and biasing circuitry 638 and injected into the amplifier driver stage 650. FIG. 6C illustrates the LPF and biasing circuitry 638 in more detail. The LPF and biasing circuitry 638 includes a CMOS switch M1 which is used as a variable resistor in series with the amplifier circuitry 640 (note that the footprint capacitances C.sub.F1 and C.sub.F2 are associated with the microcontroller). The LPF and biasing circuitry 638 includes a replica of oscillator output voltage A′, second CMOS switch M2 (which is a replica of M1), Isource (which is a constant current from a current mirror), and Isink (which is the current from the current mirror that can be switched on or off by the timer circuit). It can be seen that the gate of M1 will be one Vth higher than the oscillator output voltage when Isink is off).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Oomori et al by providing a margin testing circuit which includes a voltage detector as taught by Jefremow et al (paragraphs [0035-[0039]).
One of the ordinary skill in the art would have been motivated to make such a modification so that the voltage detector sets an amplitude flag when the oscillator signal's amplitude is higher than a predefined threshold value, which is controlled by the reference value VREF. Thus, in this example, the voltage detector 532 is the detection circuitry and the amplitude flag is the quality indicator. The control and monitor circuitry 534 monitors the amplitude flag to determine whether the oscillator signal is satisfactory. The control and monitor circuitry 534 determines the negative resistance margin based on the value of the resistance control signal at the time the amplitude flag is reset, as taught by Jefremow et al (paragraph [0037]).
Regarding dependent claim 18, Oomori (US 2022/0173698 A1) et al and Jefremow et al (US 2022/0131499 A1) the system as in claim 13.
Oomori (US 2022/0173698 A1) et al further teaches providing first and second bias (paragraphs [0032]-[0035],[0041], [0046]).
Oomori (US 2022/0173698 A1) et al is silent about, wherein the device comprises a programable current mirror to provide the first current bias from the first current reference to the driver input and to provide a second current bias from the first current reference to the driver input, wherein the first and second current biases are to produce the first voltage and a second voltage at the driver output, respectively, that are within a linear region of the voltage transfer curve of the crystal driver.
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Jefremow et al (US 2022/0131499 A1) teaches, (figures 5A-5C, paragraphs [0035]-[0039], [0040] FIG. 6A illustrates an exemplary oscillator system 600 that supports negative resistance margin testing in which resistance control circuitry includes a PWM signal generator. Amplifier circuitry 640 includes three gain stages A1, A2, and A3. The output stage A3 is a PWM controlled gain stage that serves as variable resistance circuitry 650. In other examples a different amplifier stage may serve as variable resistance circuitry 650. PWM circuitry 636 generates a PWM signal that has a variable duty cycle to control the gain of the amplifier stage 650. In one example, the PWM circuitry 636 includes a generic timer module (GTM) which is a common component found in many automotive microcontrollers.[0042] Detection circuitry 632 (e.g., PLL or voltage detector), which may be implemented on the oscillator circuit 610 or external to the oscillator circuit, monitors the oscillator signal and generates a quality indicator that indicates a satisfactory oscillator signal or an unsatisfactory oscillator signal. The control and monitor circuitry 634 monitors the quality indicator to determine whether the oscillator signal is satisfactory. The control and monitor circuitry 634 determines the negative resistance margin based on the duty cycle of the resistance control signal at the time the quality indicator indicates an unsatisfactory oscillator signal. The control and monitor circuitry 634 outputs a margin signal that communicates the determined negative resistance margin. [0043] FIG. 6B illustrates an exemplary PWM controlled amplifier driver stage 650. The PWM resistance control signal, which may be generated by a software-controlled GTM, is first processed by a low pass filter (LPF) and biasing circuitry 638 and injected into the amplifier driver stage 650. FIG. 6C illustrates the LPF and biasing circuitry 638 in more detail. The LPF and biasing circuitry 638 includes a CMOS switch M1 which is used as a variable resistor in series with the amplifier circuitry 640 (note that the footprint capacitances C.sub.F1 and C.sub.F2 are associated with the microcontroller). The LPF and biasing circuitry 638 includes a replica of oscillator output voltage A′, second CMOS switch M2 (which is a replica of M1), Isource (which is a constant current from a current mirror), and Isink (which is the current from the current mirror that can be switched on or off by the timer circuit). It can be seen that the gate of M1 will be one Vth higher than the oscillator output voltage when Isink is off).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Oomori et al by providing a margin testing circuit which includes a voltage detector as taught by Jefremow et al (paragraphs [0035-[0039]).
One of the ordinary skill in the art would have been motivated to make such a modification so that the voltage detector sets an amplitude flag when the oscillator signal's amplitude is higher than a predefined threshold value, which is controlled by the reference value VREF. Thus, in this example, the voltage detector 532 is the detection circuitry and the amplitude flag is the quality indicator. The control and monitor circuitry 534 monitors the amplitude flag to determine whether the oscillator signal is satisfactory. The control and monitor circuitry 534 determines the negative resistance margin based on the value of the resistance control signal at the time the amplitude flag is reset, as taught by Jefremow et al (paragraph [0037]).
Regarding dependent claim 19, Oomori (US 2022/0173698 A1) et al and Jefremow et al (US 2022/0131499 A1) the system as in claim 18.
Oomori (US 2022/0173698 A1) et al further teaches, wherein the voltage measuring instrument is to measure the second voltage at the driver output when the second current bias is provided to the driver input (paragraphs [0046][0047], [0065]).
Oomori et al does not explicitly teach a voltage measuring instrument but teaches, input voltage Vin and output current Iout in paragraph [0043]).
Jefremow et al (US 2022/0131499 A1) teaches, (figures 5A-5C, paragraphs [0035]-[0039], [0040] FIG. 6A illustrates an exemplary oscillator system 600 that supports negative resistance margin testing in which resistance control circuitry includes a PWM signal generator. Amplifier circuitry 640 includes three gain stages A1, A2, and A3. The output stage A3 is a PWM controlled gain stage that serves as variable resistance circuitry 650. In other examples a different amplifier
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stage may serve as variable resistance circuitry 650. PWM circuitry 636 generates a PWM signal that has a variable duty cycle to control the gain of the amplifier stage 650. In one example, the PWM circuitry 636 includes a generic timer module (GTM) which is a common component found in many automotive microcontrollers. [0042] Detection circuitry 632 (e.g., PLL or voltage detector), which may be implemented on the oscillator circuit 610 or external to the oscillator circuit, monitors the
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oscillator signal and generates a quality indicator that indicates a satisfactory oscillator signal or an unsatisfactory oscillator signal. The control and monitor circuitry 634 monitors the quality indicator to determine whether the oscillator signal is satisfactory. The control and monitor circuitry 634 determines the negative resistance margin based on the duty cycle of the resistance control signal at the time the quality indicator indicates an unsatisfactory oscillator signal. The control and monitor circuitry 634 outputs a margin signal that communicates the determined negative resistance margin. [0043] FIG. 6B illustrates an exemplary PWM controlled amplifier driver stage 650. The PWM resistance control signal, which may be generated by a software-controlled GTM, is first processed by a low pass filter (LPF) and biasing circuitry 638 and injected into the amplifier driver stage 650. FIG. 6C illustrates the LPF and biasing circuitry 638 in more detail. The LPF and biasing circuitry 638 includes a CMOS switch M1 which is used as a variable resistor in series with the amplifier circuitry 640 (note that the footprint capacitances C.sub.F1 and C.sub.F2 are associated with the microcontroller). The LPF and biasing circuitry 638 includes a replica of oscillator output voltage A′, second CMOS switch M2 (which is a replica of M1), Isource (which is a constant current from a current mirror), and Isink (which is the current from the current mirror that can be switched on or off by the timer circuit). It can be seen that the gate of M1 will be one Vth higher than the oscillator output voltage when Isink is off).
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Oomori et al by providing a margin testing circuit which includes a voltage detector as taught by Jefremow et al (paragraphs [0035-[0039]).
One of the ordinary skill in the art would have been motivated to make such a modification so that the voltage detector sets an amplitude flag when the oscillator signal's amplitude is higher than a predefined threshold value, which is controlled by the reference value VREF. Thus, in this example, the voltage detector 532 is the detection circuitry and the amplitude flag is the quality indicator. The control and monitor circuitry 534 monitors the amplitude flag to determine whether the oscillator signal is satisfactory. The control and monitor circuitry 534 determines the negative resistance margin based on the value of the resistance control signal at the time the amplitude flag is reset, as taught by Jefremow et al (paragraph [0037]).
Regarding dependent claim 20, Oomori (US 2022/0173698 A1) et al and Jefremow et al (US 2022/0131499 A1) teach the system as in claim 13,
Oomori (US 2022/0173698 A1) et al is silent, wherein measuring the first voltage on the driver output comprises measuring with an external voltage instrument having an accuracy of +/- 100mV.
However commercial oscilloscopes (Tektronix 7 series) or Keithley SMU (source measurement units 24XX series) are capable of measuring voltages of the order of microvolts and nanovolts.
Therefore it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention, to have modified the teachings of Oomari et al by providing an external voltage instrument having high accuracy such as a Tektronix or a voltage measuring instrument like an SMU or a Keithley nanovoltmeter.
One of the ordinary skill in the art would have been motivated to make such a modification so that an accurate voltage measurement can be performed.
Closest Prior art
9. The following relevant prior art of record is not cited in the office action.
Fulton et al (US 2003/0122629 A1) An oscillator circuit including an integrated circuit amplifier, an integrated circuit active resistance circuit to set the gain of the amplifier, a crystal resonator to set the frequency of the signal generated by the oscillator circuit, and a pair of capacitors respectively situated at the inputs and outputs of the amplifier to assist in the starting of the oscillation signal. The active resistance circuit is responsive to an input signal in order to set the gain of the amplifier slightly above unity gain in order to meet the criterion for oscillation, but not too much above unity gain where the oscillator would unduly consume too much power. Thus, the oscillator has inherent low power characteristics. The active resistance circuit allows the amplifier gain to be set by software or other electronic means.
Gilbert et al (US 5999062 A) teaches, A crystal oscillator drive circuit controls the maximum amplitude of the drive signal to a crystal by limiting the bias current of a gm cell which senses the oscillation amplitude of the crystal. The bias current is commutated by the gm cell responsive to the crystal oscillation. The commuted current is converted to a single-ended current by a current mirror. An output stage converts the current to an output voltage having a voltage swing that is determined by the resistance of a load resistor. The output voltage is then fed back to drive the crystal through a positive feedback path. The output voltage swing and the drive signal to the crystal are limited by the bias current of the gm cell. A fully complementary implementation of the drive circuit includes two complementary gm cells, two current mirrors, and an output stage having two load resistors. The complementary implementation is self biasing from the supply voltage and provides a symmetric topology that reduces crystal loading by cancelling the base currents in the gm cells. Unbalanced current mirrors having high current gain are utilized to provide a wide output voltage swing while reducing crystal loading by reducing the bias currents in the gm cells.
Sibrai et al (US 6741137 B1) teaches, A highly stable single chip resonator controlled oscillator with automatic gain control designed for manufacture in monolithic integrated circuit technologies. An automatic gain controller monitors the output of a crystal controlled oscillator amplifier and produces a feedback signal to ensure oscillation is induced at startup and that the amplitude of oscillation is continuously controlled during operation to reach low phase noise and reduce power consumption of the circuit.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SURESH RAJAPUTRA whose telephone number is (571) 270-0477. The examiner can normally be reached between 8:00 AM - 5:00 PM.
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/SURESH K RAJAPUTRA/Examiner, Art Unit 2858
/EMAN A ALKAFAWI/Supervisory Patent Examiner, Art Unit 2858 6/9/2026
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