DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Group I, FIG. 2 (claims 1-7, 12-16, and 18-20) in the reply filed on 8/12/26 is acknowledged.
Claims 8-11, 17, and 21 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8/12/26.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 16, and 18 thru 20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In lines 9-10 of claim 16, the applicant states “adhered surface of the insulating film”;
however, it is unclear what actual layers are being referred to when the applicant states “adhered” in the limitation “adhered surface.” Appropriate clarification and/or correction are required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 7, 12, 14, and 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bernhardt et al. US 5,933,712 A1 in view of “3 Z-Axis Adhesive Film”, 1 March 2003 as disclosed by the IDS filed 4/11/25. Bernhardt discloses (see, for example, FIG. 4) a semiconductor package comprising: a package substrate 41 having a plurality of substrate pads 44/45; a chip stack including a plurality of semiconductor chips 40 stacked on the package substrate 41, each of the plurality of semiconductor chips 40 having a plurality of chip pads 42/43; and a multichannel film 46/47 having a plurality of channels respectively connecting the plurality of chip pads 42/43 of the plurality of semiconductor chips 40 in a stacking direction, the plurality of channels electrically connected to the plurality of substrate pads 44/45, wherein the multichannel film 46/47 includes (see, for example, FIG. 2), an insulating film 21 having a first surface and a second surface located opposite to each other, a plurality of conductive lines 22 extending on the first surface of the insulating film 21 in the stacking direction, respectively having a portion protruding from the first surface of the insulating film 21, and respectively provided as the plurality of channels, and an anisotropic conductive film (see, for example, column 2, lines 43-46) including an adhesive layer on the first surface of the insulating film to cover the plurality of conductive lines, and conductive particles dispersed in the adhesive layer, the conductive particles being disposed between the plurality of conductive lines 22 and the plurality of chip pads 42/43 and electrically connecting the plurality of conductive lines 22 and the plurality of chip pads 42/43. In column 2, lines 43-46, Bernhardt discloses that the flex cables 46/47, which are comprised (see, for example, FIG. 2) of an insulating film 21, and conductive lines 22, being attached to an ACA layer, which is an anisotropically conducting adhesive. Bernhardt does not clearly disclose an anisotropic conductive film including an adhesive layer on the first surface of the insulating film to cover the plurality of conductive lines, and conductive particles dispersed in the adhesive layer. However, “3 Z-Axis Adhesive Film”, 1 March 2003” discloses anisotropically conducting adhesives contain conductive particles in an adhesive layer. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have an anisotropic conductive film including an adhesive layer on the first surface of the insulating film to cover the plurality of conductive lines, and conductive particles dispersed in the adhesive layer in order to keep an electrical connection while insulating the sides of the semiconductor package, and therefore, protect the semiconductor package.
Regarding claim 7, see, for example, FIG. 4, and column 2, lines 43-36 wherein
Bernhardt discloses the multichannel film extends to the plurality of substrate pads 44/45, and the plurality of conductive lines 22 being electrically connected to the plurality of substrate pads 44/45 by the anisotropic conductive film ACA.
Regarding claim 12, Bernhardt does not specifically disclose the plurality of conductive
lines being arranged at substantially the same pitch as the plurality of chip pads; however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the plurality of conductive lines are arranged at substantially the same pitch as the plurality of chip pads in order to keep a uniform structure, which includes easier processing and better compactness.
Regarding claim 14, Bernhardt does not specifically disclose the plurality of chip pads
being arranged at a pitch of 150 µm or less along one edge of an upper surface of each of the plurality of semiconductor chips; however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have the plurality of chip pads
being arranged at a pitch of 150 µm or less along one edge of an upper surface of each of the plurality of semiconductor chips in order to make uniform connections to the chips pads with an adequate distance therebetween according to the preferences of the user, and since it has been held that discovering an optimum value of a result effective value involves only routine skill in the art. In re Boesch, 617 F. 2d 272, 205 USPQ 215 (CCPA 1980).
Regarding claim 15, see, for example, column 2, lines 22 wherein Bernhardt discloses
each of the plurality of semiconductor chips being a semiconductor memory chip.
Claim(s) 2 thru 5 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bernhardt et al. US 5,933,712 A1 in view of “3 Z-Axis Adhesive Film”, 1 March 2003 as applied to claims 1, 7, 12, 14, and 15 above, and further in view of Beilstein, Jr. et al. US 5,517,057. Bernhardt in view of “3 Z-Axis Adhesive Film”, 1 March 2003 does not disclose each of the plurality of semiconductor chips further includes a plurality of pad extensions extending from the plurality of chip pads to an adjacent side surface to the one edge. However, Beilstein, Jr. discloses (see, for example, FIG. 29) a semiconductor package comprising chip pads 17 that contain a plurality of pad extensions 38. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have each of the plurality of semiconductor chips further includes a plurality of pad extensions extending from the plurality of chip pads to an adjacent side surface to the one edge in order to strengthen the connection to the multichannel film with semiconductor chips within the semiconductor package.
Regarding claim 3, see, for example, FIG. 4 wherein Bernhardt discloses each of the
plurality of pad extensions 38 has a portion protruding from the adjacent side surface.
Regarding claim 4, see, for example, FIG. 4 wherein Bernhardt discloses the plurality of semiconductor chips 40 being stacked such that the adjacent respective side surfaces are substantially coplanar with each other.
Regarding claim 5, see, for example, FIG. 4 wherein Bernhardt discloses the adjacent side surfaces of each of the plurality of semiconductor chips 40 have a surface perpendicular to the upper surface.
Claim(s) 6 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bernhardt et al. US 5,933,712 A1 in view of “3 Z-Axis Adhesive Film”, 1 March 2003 in view of Beilstein, Jr. et al. US 5,517,057 as applied to claims 2-5 above, and further in view of Haba et al. US 2008/0083977 A1. Bernhardt in view of “3 Z-Axis Adhesive Film”, 1 March 2003 in view of Beilstein does not disclose the substantially coplanar adjacent side surfaces of each of the plurality of semiconductor chips form an upward inclined surface. However, Haba discloses (see, for example, FIG. 28) a semiconductor package comprising the substantially coplanar adjacent side surfaces of each of the plurality of semiconductor chips 210 form an upward inclined surface. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have substantially coplanar adjacent side surfaces of each of the plurality of semiconductor chips form an upward inclined surface in order to save space and, therefore, increase the robustness of a semiconductor device.
In view of the 112 rejection above, claim(s) 16, and 18 thru 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Bielstein, Jr. et al. 5,517,057 in view of Imai US 2004/042509 A1. Bielstein, Jr. discloses (see, for example, FIG. 29) a semiconductor package comprising: a chip stack including a plurality of semiconductor chips 11, each semiconductor chip 11 having a plurality of chip pads 17 arranged along one edge of a respective upper surface and pad extensions 38 extending from the plurality of chip pads 17 to an adjacent side surface of the one edge, the plurality of semiconductor chips 11 being stacked such that the adjacent side surfaces have a coplanar surface; and a multichannel film 25/26 having an insulating film 26 adhered to the adjacent side surfaces of the plurality of semiconductor chips 11, and a plurality of conductive lines 25 disposed on an adhered surface of the insulating film 26 and connecting the chip pads 17 of the plurality of respective semiconductor chips 11 in a stacking direction. Bielstein, Jr. does not clearly disclose a package substrate having a plurality of substrate pads. However, Imai discloses (see, for example, FIG. 14) a semiconductor package comprising a package substrate 80 having plurality of substrate pads 82. It would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have a package substrate having a plurality of substrate pads in order to provide mechanical support and make other connections outside of the semiconductor package.
Regarding claim 18, see, for example, FIG. 29 wherein Beilstein, Jr. discloses each of the plurality of conductive lines 25 has a first protruding portion from the adhered surface of the insulating film 26, and each of the plurality of pad extensions 38 has a second protruding portion from the adjacent side surface.
Regarding claim 19, see, for example, FIG. 29 wherein Beilstein, Jr. discloses the plurality of conductive lines 25 are arranged at substantially the same pitch as the plurality of chip pads 17. Beilstein, Jr. in view Imai does not disclose each conductive line of the plurality of conductive lines has a width equal to or smaller than a width of each of the plurality of pad extensions; however, it would have been obvious to one of ordinary skill in the art, at a time prior to the effective filing date, to have each conductive line of the plurality of conductive lines has a width equal to or smaller than a width of each of the plurality of pad extensions in order to minimize the size of the semiconductor package, and therefore, increase its robustness.
Regarding claim 20, see, for example, FIG. 14 wherein Imai discloses a multichannel film 88/90 extends to the substrate pads 82 on the package substrate 80, and the plurality of conductive lines 90 are electrically connected to the substrate pads 82.
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to EUGENE LEE whose telephone number is (571)272-1733. The examiner can normally be reached M-F 730-330 PM.
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Eugene Lee
August 26, 2026
/EUGENE LEE/Primary Examiner, Art Unit 2815
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