DETAILED ACTION
This action is responsive to the application filed June 17, 2024. Claims 1-20 are pending. Claims 1, 9, and 15 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
Acknowledgment is made of applicant’s Information Disclosure Statement (IDS) filed on June 17, 2024. This IDS has been considered.
Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because the quality of Figures 1-6, on the Record, is degraded because of the use of what appears to be greyscale instead of only black. Applicant is advised that drawings must be black and white, and 37 C.F.R. 1.84(l) states, “All drawings must be made by a process which will give them satisfactory reproduction characteristics. Every line, number, and letter must be durable, clean, black (except for color drawings), sufficiently dense and dark, and uniformly thick and well-defined. The weight of all lines and letters must be heavy enough to permit adequate reproduction. This requirement applies to all lines however fine, to shading, and to lines representing cut surfaces in sectional views. Lines and strokes of different thicknesses may be used in the same drawing where different thicknesses have a different meaning.”
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Interpretation
Regarding the claim elements “first/second/third corrective read voltage signals” as recited in claims 1, 6-9, 13, 15, 17, and 19-20, only the applying of these signals to various word lines of the apparatus in certain proximate locations and under certain conditions is recited in the specification. Additionally, these elements appear to be directed to Figs. 3A, 3B, and 4.
There are no measurable specific electrical characteristics to differentiate between these three elements which are disclosed in applicant’s specification other than para. 67: “a magnitude of the first corrective read voltage signal can be lowered in response to the target word line being a boundary word line (emphasis added)”, and visually comparing the complex waveforms of VCRS1 and VCRS2 in the diagram of Fig. 4.
It is noted that the plain meaning of the term “can be lowered” in para. 67 does not differentiate the first corrective read voltage signal as the unmodified signal magnitude is not specified, and moreover “can be” necessarily does not mean “must be” or “is” lowered.
The complex waveform diagrams for VCRS1 and VCRS2 of Fig. 4 have no axis labels or units nor are the timing, period, pulse width, fall/rise time of the numerous amplitude spikes able to be evinced. Not to mention that VCRS3 is not depicted at all. Therefore, Fig. 4 also provides no patentable differentiation.
The notion of a “read voltage” in general is well understood in the art and therefore can be considered definite. However, any supposed modifications to the read voltage making the signals in the instant application “corrective” is ambiguous and does not allow one of ordinary skill in the art to distinguish between them and a nominal read voltage signal. MPEP 2173.02(II) instructs examiners that the metes and bounds of the claim must be determined with sufficient precision to provide others as to what constitutes infringement.
For these reasons, as per MPEP 2111.01, the phrase “first/second/third corrective read voltage signals” will be understood for examination given its broadest reasonable interpretation to mean “a read voltage signal that is merely different in any manner from the nominal read voltage signal”.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-4, and 6-14 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka (US 20230178155) in view of Kim et al. (US 20170004885; “Kim”).
Regarding independent claim 1, Tanaka discloses an apparatus, comprising:
an array of memory cells (Fig. 1B: array of memory cells 104);
a controller coupled to the array of memory cells (Fig. 1B: controller 135)
and the controller is configured to:
perform a corrective read operation on a target word line of a partially programmed block (para. 18; "corrective read voltages can be applied that correspond to two conditions, either both neighbor cells are erased or at least one neighbor cell is programmed". It is noted that the Tanaka's condition of "at least one neighbor cell is programmed" necessarily indicates that the block is partially programmed),
wherein the corrective read operation includes:
applying a first corrective read voltage signal to the target word line during the corrective read operation (para. 16 "the selected memory cell is read with a read voltage applied to a gate electrode of the selected memory cell", "the read voltage (e.g., a corrective read voltage) is adjusted");
applying a second corrective read voltage signal to a word line adjacent to the target word line during the corrective read operation (para. 61; "the control logic (e.g., the corrective reader 137) causes a first voltage (V.sub.H) to be applied to the first wordline WLn of the selected memory cell 510 and causes a second voltage (V.sub.L) to be applied to the wordlines adjacent to the first wordline");
Tanaka is silent with respect to any pass voltages applied.
However, Kim teaches applying a first pass voltage to a number of unprogrammed word lines of the partially programmed block during the corrective read operation (para. 9; “a second pass voltage lower than the first pass voltage is applied to word lines coupled to non-programmed pages among the pages that are not selected for the read operation");
and applying a second pass voltage to a first number of programmed word lines of the partially programmed block that are nonadjacent to the target word line during the corrective read operation (para. 9; "a first pass voltage is applied to word lines coupled to the programmed pages among pages that are not selected for the read operation").
Tanaka and Kim are from the same field of endeavor as applicant’s invention directed to performing memory operations on non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Tanaka’s corrective read with the teachings of Kim’s two level pass voltage to perform read operations on partially programmed blocks. Doing so would reduce the back pattern effect while improving memory densities.
Regarding claim 2, Tanaka and Kim combined disclose the limitations of claim 1.
As applied, Kim further discloses wherein the partially programmed block comprises a number of programmed word lines that include the number of inner word lines and a boundary word line. (Fig. 6 where it illustrates the programmed word line group GR_P, with a boundary word line (WL2) and inner word lines (WL1, WL0)).
Regarding claim 3, Tanaka and Kim combined disclose the limitations of claim 2.
As applied, Kim further discloses wherein the partially programmed block comprises the number of unprogrammed word lines (Fig. 6 where it illustrates the unprogrammed word line group GR_E)
and wherein a first unprogrammed word line of the number of unprogrammed word lines is adjacent to the boundary word line. (Fig. 6 where it illustrates the first unprogrammed word line (WL3) is adjacent to the boundary word line (WL2)).
Regarding claim 4, Tanaka and Kim combined disclose the limitations of claim 1.
As applied, Kim further discloses wherein a magnitude of the first pass voltage is less than a magnitude of the second pass voltage (para. 9 "a second pass voltage lower than the first pass voltage is applied to word lines". It is noted that the lower first pass voltage of the instant application is applied to the unprogrammed word lines and is analogous to Kim's second pass voltage).
Regarding claim 6, Tanaka and Kim combined disclose the limitations of claim 1.
As applied, Tanaka further discloses wherein the second corrective read voltage signal is applied to the word line adjacent to the target word line during a 1 bit corrective read operation (para. 61; "the control logic (e.g., the corrective reader 137) causes a first voltage (V.sub.H) to be applied to the first wordline WLn of the selected memory cell 510 and causes a second voltage (V.sub.L) to be applied to the wordlines adjacent to the first wordline". See also para. 30; "Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single level cells (SLC) can store one bit per cell". It is noted that the instant application discloses that a 1 bit corrective read is associated with SLC memory cells).
Regarding claim 7, Tanaka and Kim combined disclose the limitations of claim 1.
As applied, Tanaka further discloses wherein the second corrective read voltage signal is applied to the word line adjacent to the target word line during a 2 bit corrective read operation (para. 61; "the control logic (e.g., the corrective reader 137) causes a first voltage (V.sub.H) to be applied to the first wordline WLn of the selected memory cell 510 and causes a second voltage (V.sub.L) to be applied to the wordlines adjacent to the first wordline". See also para. 30; "Each of the memory devices 130 can include one or more arrays of memory cells.", "In some embodiments, a particular memory device can include an SLC portion, and an MLC portion. It is noted that the instant application discloses that a 2 bit corrective read is associated with MLC memory cells).
Regarding claim 8, Tanaka and Kim combined disclose the limitations of claim 1.
As applied, Tanaka further discloses wherein a third corrective read voltage signal is applied to another word line adjacent to the target word line during a 2 sided corrective read operation (Fig. 5A & 5B where it illustrates corrective read voltages applied to word lines on both adjacent sides (e.g.: 2 sided) of the target word line WLn).
Regarding independent claim 9, Tanaka discloses an apparatus, comprising:
an array of memory cells (Fig. 1B: array of memory cells 104);
a controller coupled to the array of memory cells (Fig. 1B: controller 135)
and the controller is configured to:
perform a corrective read operation on a boundary word line of a partially programmed block (para. 18; "corrective read voltages can be applied that correspond to two conditions, either both neighbor cells are erased or at least one neighbor cell is programmed". It is noted that the Tanaka's condition of "at least one neighbor cell is programmed" necessarily indicates that the block is partially programmed and wherever the programmed cell is adjacent to the unprogrammed cell would necessarily be considered the boundary word line),
wherein the corrective read operation includes:
applying a first corrective read voltage signal to the boundary word line of the partially programmed block during a read operation on the boundary word line (para. 18; "corrective read voltages can be applied", "at least one neighbor cell is programmed". It is noted that the Tanaka's condition of "at least one neighbor cell is programmed" necessarily indicates that the word line is a boundary word line);
applying a second corrective read voltage signal to a word line adjacent to the boundary word line during the corrective read operation (para. 61; "the control logic (e.g., the corrective reader 137) causes a first voltage (V.sub.H) to be applied to the first wordline WLn of the selected memory cell 510 and causes a second voltage (V.sub.L) to be applied to the wordlines adjacent to the first wordline");
Tanaka is silent with respect to any pass voltages applied.
However, Kim teaches applying a first pass voltage to a number of unprogrammed word lines of the partially programmed block during the corrective read operation (para. 9; "a second pass voltage lower than the first pass voltage is applied to word lines coupled to non-programmed pages among the pages that are not selected for the read operation");
and applying a second pass voltage to a first number of programmed word lines of the partially programmed block that are nonadjacent to the boundary word line (para. 9 "a first pass voltage is applied to word lines coupled to the programmed pages among pages that are not selected for the read operation").
Tanaka and Kim are from the same field of endeavor as applicant’s invention directed to performing memory operations on non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Tanaka’s corrective read with the teachings of Kim’s two level pass voltage to perform read operations on partially programmed blocks. Doing so would reduce the back pattern effect while improving memory densities.
Regarding claim 10, Tanaka and Kim combined disclose the limitations of claim 9.
As applied, Kim further discloses wherein the partially programmed block comprises a number of programmed word lines that include the inner word line, the first number of inner word lines, and the boundary word line (Fig. 6 where it illustrates the programmed word line group GR_P, with a boundary wordline (WL2) and inner wordlines (WL1, WL0)).
Regarding claim 11, Tanaka and Kim combined disclose the limitations of claim 10.
As applied, Kim further discloses wherein the partially programmed block comprises the number of unprogrammed word lines and the unprogrammed word line adjacent to the boundary word line (Fig. 6 where it illustrates the unprogrammed word line group GR_E, of which unprogrammed word line WL3 is adjacent to boundary word line WL2).
Regarding claim 12, Tanaka and Kim combined disclose the limitations of claim 9.
As applied, Kim further discloses wherein a magnitude of the first pass voltage is less than a magnitude of the second pass voltage (para. 9; "a second pass voltage lower than the first pass voltage is applied to word lines coupled to non-programmed pages among the pages that are not selected for the read operation". As noted previously, while Kim's first and second pass voltage nomenclature is reversed from that of the instant application, the magnitude relationship is the same).
Regarding claim 13, Tanaka and Kim combined disclose the limitations of claim 9.
As applied, Tanaka further discloses wherein a magnitude of the first corrective read voltage signal applied to the boundary word line is less than a magnitude of a corrective read voltage signal applied to an inner word line of the partially programmed block during a corrective read operation on the inner word line. (abstr. "a corrective read operation to be performed at a selected memory cell. The operations include: causing a first voltage to be applied to a first wordline associated with the selected memory cell; causing a second voltage, having a lower magnitude than the first voltage, to be applied to wordlines adjacent to the first wordline").
Regarding claim 14, Tanaka and Kim combined disclose the limitations of claim 9.
As applied, Kim further discloses wherein the corrective read operation on the boundary word line is a 1-sided corrective read operation (Fig. 6 where it illustrates that the boundary wordline WL2 is adjacent to the unprogrammed word lines of the block. It would necessarily be irrelevant to attempt to perform a corrective read operation on an unprogrammed word line, and therefore only one sided).
Claims 5, and 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka (US 20230178155) in view of Kim et al. (US 20170004885; “Kim”) and further in view of Peleato et al. ("Adaptive Read Thresholds for NAND Flash"; “Peleato”).
Regarding claim 5, Tanaka and Kim combined disclose the limitations of claim 1.
While Tanaka and Kim combined disclose the feature of corrective read operations, and both apparatuses include the feature of error correcting code circuitry, they are silent with respect to the explicit causality connection.
However, Peleato teaches wherein the corrective read operation is performed in response to a bit error count of a prior read operation on the target word line being above a threshold amount (pg. 3069, col. 2; "Typically, all post-read signal processing algorithms require re-reads using different thresholds", "finding optimal read thresholds in a dynamic manner to minimize BER and speed up the post-processing is essential". It is noted that Peleato's "re-read" is analogous to the "corrective read operation" of the instant application. Additionally, optimizing by minimizing bit error rate (BER) indicates that the re-read post processing is due to bit errors exceeding a threshold ).
Regarding independent claim 15, Tanaka discloses a method, comprising:
receiving a corrective read command (para. 38; "control logic of the local media controller 135 includes a corrective reader 137 configured to implement or direct the program operations and other related operations discussed herein for performing a fast two-sided corrective read operation.")
determining the corrective read command is for data on a partially programmed block (para. 18; "corrective read voltages can be applied that correspond to two conditions, either both neighbor cells are erased or at least one neighbor cell is programmed". It is noted that the Tanaka's condition of "at least one neighbor cell is programmed" necessarily indicates that the block is partially programmed);
performing a corrective read operation on a target word line of the partially programmed block by:
applying a first of corrective read voltage signal to the target word line during the corrective read operation on the target word line of the partially programmed block (para. 16 "the selected memory cell is read with a read voltage applied to a gate electrode of the selected memory cell", "the read voltage (e.g., a corrective read voltage) is adjusted");
applying a second corrective read voltage signal to a word line adjacent to the target word line during the corrective read operation (para. 61; "the control logic (e.g., the corrective reader 137) causes a first voltage (V.sub.H) to be applied to the first wordline WLn of the selected memory cell 510 and causes a second voltage (V.sub.L) to be applied to the wordlines adjacent to the first wordline");
Tanaka does not disclose that the corrective read operation is an explicit result of error correcting code operations or the resulting applying of various pass voltages.
However, Paleato teaches in response to a bit error count of a read operation being above a threshold amount (pg. 3069, col. 2; "Typically, all post-read signal processing algorithms require re-reads using different thresholds", "finding optimal read thresholds in a dynamic manner to minimize BER and speed up the post-processing is essential". It is noted that Peleato's "re-read" is analogous to the "corrective read operation" of the instant application. Additionally, optimizing by minimizing bit error rate (BER) indicates that the re-read post processing is due to bit errors exceeding a threshold);
And Kim teaches applying a first pass voltage to a number of unprogrammed word lines of the partially programmed block during the corrective read operation (para. 9; "a second pass voltage lower than the first pass voltage is applied to word lines coupled to non-programmed pages among the pages that are not selected for the read operation");
and applying a second pass voltage to a first number of programmed word lines of the partially programmed block that are nonadjacent to the target word line during the corrective read operation. (para. 9; "a first pass voltage is applied to word lines coupled to the programmed pages among pages that are not selected for the read operation")
Tanaka, Peleato, and Kim are from the same field of endeavor as applicant’s invention directed to performing memory read operations on non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Tanaka’s corrective read based on the teachings of Peleato's BER reduction and along with Kim’s two level pass voltage to perform read operations on partially programmed blocks. Doing so would reduce the number of read retries required for read errors speeding up the memory device.
Regarding claim 16, Tanaka, Kim and Peleato combined disclose the limitations of claim 15
As applied, Kim further discloses wherein a magnitude of the first pass voltage is less than a magnitude of the second pass voltage (para. 9; "a second pass voltage lower than the first pass voltage is applied to word lines coupled to non-programmed pages among the pages that are not selected for the read operation". As noted previously, while Kim's first and second pass voltage nomenclature is reversed from that of the instant application, the magnitude relationship is the same).
Regarding claim 17, Tanaka, Kim and Peleato combined disclose the limitations of claim 15.
As applied, Tanaka further discloses The method of wherein a magnitude of the first corrective read voltage signal is lowered in response to the target word line being a boundary word line (abstr. "a corrective read operation to be performed at a selected memory cell. The operations include: causing a first voltage to be applied to a first wordline associated with the selected memory cell; causing a second voltage, having a lower magnitude than the first voltage, to be applied to wordlines adjacent to the first wordline").
Regarding claim 18, Tanaka, Kim and Peleato combined disclose the limitations of claim 15.
As applied, Kim further discloses wherein the partially programmed block comprises a number of programmed word lines that include the number of inner word lines and a boundary word line (Fig. 6 where it illustrates the programmed word line group GR_P, with a boundary wordline (WL2) and inner wordlines (WL1, WL0))
and wherein the partially programmed block comprises the number of unprogrammed word lines (Fig. 6 where it illustrates the unprogrammed word line group GR_E)
and wherein a first unprogrammed word line of the number of unprogrammed word lines is adjacent to the boundary word line (Fig. 6 where it illustrates the first unprogramed word line (WL3) is adjacent to the boundary wordline (WL2)).
Regarding claim 19, Tanaka, Kim and Peleato combined disclose the limitations of claim 15.
As applied, Tanaka further discloses further including applying the second corrective read voltage signal to the word line adjacent to the target word line during a 1 bit corrective read operation (para. 61; "the control logic (e.g., the corrective reader 137) causes a first voltage (V.sub.H) to be applied to the first wordline WLn of the selected memory cell 510 and causes a second voltage (V.sub.L) to be applied to the wordlines adjacent to the first wordline". See also para. 30; "Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single level cells (SLC) can store one bit per cell". It is noted that the instant application discloses that a 1 bit corrective read is associated with SLC memory cells).
Regarding claim 20, Tanaka, Kim and Peleato combined disclose the limitations of claim 15.
As applied, Tanaka further discloses further including applying a third corrective read voltage signal to another word line adjacent to the target word line during a 2 sided-2 bit corrective read operation (para. 61; "the control logic (e.g., the corrective reader 137) causes a first voltage (V.sub.H) to be applied to the first wordline WLn of the selected memory cell 510 and causes a second voltage (V.sub.L) to be applied to the wordlines adjacent to the first wordline". See also para. 30; "Each of the memory devices 130 can include one or more arrays of memory cells.", "In some embodiments, a particular memory device can include an SLC portion, and an MLC portion. It is noted that the instant application discloses that a 2 bit corrective read is associated with MLC memory cells. See also Fig. 5A & 5B where it illustrates corrective read voltages applied to word lines on both adjacent sides (e.g.: 2 sided) of the target word line WLn).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lee (US 20220366989) – Use of modified read voltages and multiple read pass voltages to mitigate errors.
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/James S. Wells/Examiner, Art Unit 2825
/ALEXANDER SOFOCLEOUS/Supervisory Patent Examiner, Art Unit 2825