DETAILED ACTION
This action is responsive to the amendments filed May 29, 2026. Claims 1-20 are pending. Claims 1, 9, and 15 have been amended. Claims 1, 9, and 15 are independent.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
Applicant's amendments to the drawings is acknowledged and accepted. The objection to the drawings has been withdrawn.
Response to Amendment
Applicant's amendments have been entered. However, applicant is reminded that, pursuant to MPEP § 714.02, for a fully complete reply - "Applicant should also specifically point out the support for any amendments made to the disclosure." The present reply does not identify the portions of the original disclosure that provide support for the newly added limitations.
Nevertheless, the Examiner has exercised discretion to examine the amended claims on the merits. Upon review of the original disclosure, support is found in para. 13-14, 51-52, 60, and 63.
Claim Interpretation
Regarding the terms “first/second/third corrective read voltage signals” remain in the amended claims and are still material to the § 103 rejections. The broadest reasonable interpretation as set forth in the non-final continues to apply and has not been rendered moot by the amendments.
Claim Rejections - 35 USC § 112 - Indefiniteness
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 2, 10, 15 and 18 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Regarding claims 2, 10 and 18, the claims recite "the number of inner word lines" (emphasis added). There is insufficient antecedent basis for this limitation in these claims because base claims 1, 9, and 15 respectively do not previously introduce any "inner word lines.
Regarding independent claim 15, the claim is directed to a method of performing a corrective read operation on a target word line. However, the claim thereafter recites:
"to determine data states of memory cells on the boundary word line" (emphasis added); and
"to determine data states of memory cells on the word line adjacent to the boundary word line." (emphasis added).
There is insufficient antecedent basis for "the boundary word line" in claim 15. The claim never previously introduces a boundary word line. It is noted that the defective language in claim 15 appears to be amended residual wording carried over from claim 9 (which is properly directed to a boundary word line). Correction of claim 15 to consistently refer to the target word line (or appropriate introduction of the boundary word line) is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Tanaka (US 20230178155 – of record) in view of Kim et al. (US 20170004885; “Kim” – of record), and further in view of Peleato et al. ("Adaptive Read Thresholds for NAND Flash"; “Peleato” – of record).
Regarding independent claim 1, Tanaka discloses an apparatus, comprising:
an array of memory cells (Fig. 1B: array of memory cells 104);
a controller coupled to the array of memory cells (Fig. 1B: controller 135)
and the controller is configured to:
perform a corrective read operation on a target word line of a partially programmed block (para. 18; "corrective read voltages can be applied that correspond to two conditions, either both neighbor cells are erased or at least one neighbor cell is programmed". It is noted that the Tanaka's condition of "at least one neighbor cell is programmed" necessarily indicates that the block is partially programmed),
wherein the corrective read operation includes:
applying a first corrective read voltage signal to the target word line during the corrective read operation (para. 16 "the selected memory cell is read with a read voltage applied to a gate electrode of the selected memory cell", "the read voltage (e.g., a corrective read voltage) is adjusted") to determine data states of memory cells on the target word line (para. 17; "that determines (or estimates) the state of each neighbor memory cell of a selected memory cell before performing the read operation at the selected memory cell". It is noted that determining the data state of the target cell is the explicit reason the corrective read voltage is applied.);
applying a second corrective read voltage signal to a word line adjacent to the target word line during the corrective read operation (Fig. 5B. See also para. 61; "the control logic (e.g., the corrective reader 137) causes a first voltage (V.sub.H) to be applied to the first wordline WLn of the selected memory cell 510 and causes a second voltage (V.sub.L) to be applied to the wordlines adjacent to the first wordline") to determine data states of memory cells on the word line adjacent to the target word line (para. 17; "that determines (or estimates) the state of each neighbor memory cell of a selected memory cell before performing the read operation at the selected memory cell". It is noted that determining the data state of the target cell is the explicit reason the corrective read voltage is applied.);
Tanaka is silent with respect to any pass voltages applied.
However, Kim teaches applying a first pass voltage to a number of unprogrammed word lines of the partially programmed block during the corrective read operation (para. 9; “a second pass voltage lower than the first pass voltage is applied to word lines coupled to non-programmed pages among the pages that are not selected for the read operation". It is noted that Kim discloses the identical differential pass-voltage scheme, but labels the voltages in reverse order from the claim language. The nomenclature difference is immaterial.);
and applying a second pass voltage to a first number of programmed word lines of the partially programmed block that are nonadjacent to the target word line during the corrective read operation (para. 9; "a first pass voltage is applied to word lines coupled to the programmed pages among pages that are not selected for the read operation"),
wherein the first pass voltage has a lower magnitude than the second pass voltage (para. 9; “a second pass voltage lower than the first pass voltage is applied").
Tanaka and Kim are silent with regard to initiating the corrective read in response to a bit error count exceeding a threshold.
However, Peleato teaches in response to a bit error count of a read operation being above a threshold amount (pg. 3069, Abstr; "A primary source of increased read time on NAND flash comes from the fact that, in the presence of noise, the flash medium must be read several times using different read threshold voltages for the decoder to succeed." See also pg. 3069, Sect. I, col. 2; "In some cases, the BER is too large for a hard decoder to succeed, even if the read is done at the optimal threshold. It is then necessary to generate soft information by performing multiple reads with different read thresholds.),
Tanaka, Kim and Peleato are from the same field of endeavor as applicant’s invention directed to performing memory operations on non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the corrective-read framework of Tanaka with Kim’s differential pass voltage technique on partially programmed blocks while initiating the corrective read operation in response to a bit-error count above a threshold as taught by Peleato. Doing so would reduce the back pattern effect while improving memory densities. The combination combines known methods and yields only predictable results.
Regarding claim 2, notwithstanding the rejection for indefiniteness above, Tanaka, Kim and Peleato combined disclose the limitations of claim 1.
As applied, Kim further discloses wherein the partially programmed block comprises a number of programmed word lines that include the number of inner word lines and a boundary word line. (Fig. 6 where it illustrates the programmed word line group GR_P, with a boundary word line (WL2) and inner word lines (WL1, WL0)).
Regarding claim 3, Tanaka, Kim and Peleato combined disclose the limitations of claim 2.
As applied, Kim further discloses wherein the partially programmed block comprises the number of unprogrammed word lines (Fig. 6 where it illustrates the unprogrammed word line group GR_E)
and wherein a first unprogrammed word line of the number of unprogrammed word lines is adjacent to the boundary word line. (Fig. 6 where it illustrates the first unprogrammed word line (WL3) is adjacent to the boundary word line (WL2)).
Regarding claim 4, Tanaka, Kim and Peleato combined disclose the limitations of claim 1.
As applied, Kim further discloses wherein a magnitude of the first pass voltage is less than a magnitude of the second pass voltage (para. 9 "a second pass voltage lower than the first pass voltage is applied to word lines". It is noted that the lower first pass voltage of the instant application is applied to the unprogrammed word lines and is analogous to Kim's second pass voltage).
It is noted for the record that the limitations of claim 4 are fully recited in independent claim 1 as a result of the present amendments. Consequently, claim 4 is redundant in view of amended claim 1.
Regarding claim 5, Tanaka, Kim and Peleato combined disclose the limitations of claim 1.
As applied, Peleato further discloses wherein the corrective read operation is performed in response to a bit error count of a prior read operation on the target word line being above a threshold amount (pg. 3069, col. 2; "Typically, all post-read signal processing algorithms require re-reads using different thresholds", "finding optimal read thresholds in a dynamic manner to minimize BER and speed up the post-processing is essential". It is noted that Peleato's "re-read" is analogous to the "corrective read operation" of the instant application. Additionally, optimizing by minimizing bit error rate (BER) indicates that the re-read post processing is due to bit errors exceeding a threshold ).
Regarding claim 6, Tanaka, Kim and Peleato combined disclose the limitations of claim 1.
As applied, Tanaka further discloses wherein the second corrective read voltage signal is applied to the word line adjacent to the target word line during a 1 bit corrective read operation (para. 61; "the control logic (e.g., the corrective reader 137) causes a first voltage (V.sub.H) to be applied to the first wordline WLn of the selected memory cell 510 and causes a second voltage (V.sub.L) to be applied to the wordlines adjacent to the first wordline". See also para. 30; "Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single level cells (SLC) can store one bit per cell". It is noted that the instant application discloses that a 1 bit corrective read is associated with SLC memory cells).
Regarding claim 7, Tanaka, Kim and Peleato combined disclose the limitations of claim 1.
As applied, Tanaka further discloses wherein the second corrective read voltage signal is applied to the word line adjacent to the target word line during a 2 bit corrective read operation (para. 61; "the control logic (e.g., the corrective reader 137) causes a first voltage (V.sub.H) to be applied to the first wordline WLn of the selected memory cell 510 and causes a second voltage (V.sub.L) to be applied to the wordlines adjacent to the first wordline". See also para. 30; "Each of the memory devices 130 can include one or more arrays of memory cells.", "In some embodiments, a particular memory device can include an SLC portion, and an MLC portion. It is noted that the instant application discloses that a 2 bit corrective read is associated with MLC memory cells).
Regarding claim 8, Tanaka, Kim and Peleato combined disclose the limitations of claim 1.
As applied, Tanaka further discloses wherein a third corrective read voltage signal is applied to another word line adjacent to the target word line during a 2 sided corrective read operation (Fig. 5A & 5B where it illustrates corrective read voltages applied to word lines on both adjacent sides (e.g.: 2 sided) of the target word line WLn).
Regarding independent claim 9, Tanaka discloses an apparatus, comprising:
an array of memory cells (Fig. 1B: array of memory cells 104);
a controller coupled to the array of memory cells (Fig. 1B: controller 135)
and the controller is configured to:
perform a corrective read operation on a boundary word line of a partially programmed block (para. 18; "corrective read voltages can be applied that correspond to two conditions, either both neighbor cells are erased or at least one neighbor cell is programmed". It is noted that the Tanaka's condition of "at least one neighbor cell is programmed" necessarily indicates that the block is partially programmed and wherever the programmed cell is adjacent to the unprogrammed cell would necessarily be considered the boundary word line),
wherein the corrective read operation includes:
applying a first corrective read voltage signal to the boundary word line of the partially programmed block during a read operation on the boundary word line (para. 18; "corrective read voltages can be applied", "at least one neighbor cell is programmed". It is noted that the Tanaka's condition of "at least one neighbor cell is programmed" necessarily indicates that the word line is a boundary word line) to determine data states of memory cells on the boundary word line (para. 17; "that determines (or estimates) the state of each neighbor memory cell of a selected memory cell before performing the read operation at the selected memory cell". It is noted that the boundary word line is the selected word line in this embodiment.);
applying a second corrective read voltage signal to a word line adjacent to the boundary word line during the corrective read operation (para. 61; "the control logic (e.g., the corrective reader 137) causes a first voltage (V.sub.H) to be applied to the first wordline WLn of the selected memory cell 510 and causes a second voltage (V.sub.L) to be applied to the wordlines adjacent to the first wordline") to determine data states of memory cells on the word line adjacent to the boundary word line (para. 16; "Thus, a corrective read operation can be performed to detect whether neighbor memory cells are erased or programmed.");
Tanaka is silent with respect to any pass voltages applied.
However, Kim teaches applying a first pass voltage to a number of unprogrammed word lines of the partially programmed block during the corrective read operation (para. 9; "a second pass voltage lower than the first pass voltage is applied to word lines coupled to non-programmed pages among the pages that are not selected for the read operation");
and applying a second pass voltage to a first number of programmed word lines of the partially programmed block that are nonadjacent to the boundary word line (para. 9 "a first pass voltage is applied to word lines coupled to the programmed pages among pages that are not selected for the read operation").
wherein the first pass voltage has a lower magnitude than the second pass voltage (para. 9; “a second pass voltage lower than the first pass voltage is applied").
Tanaka and Kim are silent with regard to initiating the corrective read in response to a bit error count exceeding a threshold.
However, Peleato teaches in response to a bit error count of a read operation being above a threshold amount (pg. 3069, Abstr; "A primary source of increased read time on NAND flash comes from the fact that, in the presence of noise, the flash medium must be read several times using different read threshold voltages for the decoder to succeed." See also pg. 3069, Sect. I, col. 2; "In some cases, the BER is too large for a hard decoder to succeed, even if the read is done at the optimal threshold. It is then necessary to generate soft information by performing multiple reads with different read thresholds.),
Tanaka, Kim and Peleato are from the same field of endeavor as applicant’s invention directed to performing memory operations on non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the corrective-read framework of Tanaka with Kim’s differential pass voltage technique on partially programmed blocks while initiating the corrective read operation in response to a bit-error count above a threshold as taught by Peleato. Doing so would reduce the back pattern effect while improving memory densities. The combination combines known methods and yields only predictable results.
Regarding claim 10, notwithstanding the rejection for indefiniteness above, Tanaka and Kim combined disclose the limitations of claim 9.
As applied, Kim further discloses wherein the partially programmed block comprises a number of programmed word lines that include the inner word line, the first number of inner word lines, and the boundary word line (Fig. 6 where it illustrates the programmed word line group GR_P, with a boundary wordline (WL2) and inner wordlines (WL1, WL0)).
Regarding claim 11, Tanaka, Kim and Peleato combined disclose the limitations of claim 10.
As applied, Kim further discloses wherein the partially programmed block comprises the number of unprogrammed word lines and the unprogrammed word line adjacent to the boundary word line (Fig. 6 where it illustrates the unprogrammed word line group GR_E, of which unprogrammed word line WL3 is adjacent to boundary word line WL2).
Regarding claim 12, Tanaka, Kim and Peleato combined disclose the limitations of claim 9.
As applied, Kim further discloses wherein a magnitude of the first pass voltage is less than a magnitude of the second pass voltage (para. 9; "a second pass voltage lower than the first pass voltage is applied to word lines coupled to non-programmed pages among the pages that are not selected for the read operation". As noted previously, while Kim's first and second pass voltage nomenclature is reversed from that of the instant application, the magnitude relationship is the same).
It is noted for the record that the limitations of claim 12 are fully recited in independent claim 9 as a result of the present amendments. Consequently, claim 12 is redundant in view of amended claim 9.
Regarding claim 13, Tanaka, Kim and Peleato combined disclose the limitations of claim 9.
As applied, Tanaka further discloses wherein a magnitude of the first corrective read voltage signal applied to the boundary word line is less than a magnitude of a corrective read voltage signal applied to an inner word line of the partially programmed block during a corrective read operation on the inner word line. (Abstr. "a corrective read operation to be performed at a selected memory cell. The operations include: causing a first voltage to be applied to a first wordline associated with the selected memory cell; causing a second voltage, having a lower magnitude than the first voltage, to be applied to wordlines adjacent to the first wordline").
Regarding claim 14, Tanaka, Kim and Peleato combined disclose the limitations of claim 9.
As applied, Kim further discloses wherein the corrective read operation on the boundary word line is a 1-sided corrective read operation (Fig. 6 where it illustrates that the boundary wordline WL2 is adjacent to the unprogrammed word lines of the block. It would necessarily be irrelevant to attempt to perform a corrective read operation on an unprogrammed word line, and therefore only one sided).
Regarding independent claim 15, notwithstanding the rejection for indefiniteness above Tanaka discloses a method, comprising:
receiving a corrective read command (para. 38; "control logic of the local media controller 135 includes a corrective reader 137 configured to implement or direct the program operations and other related operations discussed herein for performing a fast two-sided corrective read operation.")
determining the corrective read command is for data on a partially programmed block (para. 18; "corrective read voltages can be applied that correspond to two conditions, either both neighbor cells are erased or at least one neighbor cell is programmed". It is noted that the Tanaka's condition of "at least one neighbor cell is programmed" necessarily indicates that the block is partially programmed);
performing a corrective read operation on a target word line of the partially programmed block by:
applying a first of corrective read voltage signal to the target word line during the corrective read operation on the target word line of the partially programmed block (para. 16 "the selected memory cell is read with a read voltage applied to a gate electrode of the selected memory cell", "the read voltage (e.g., a corrective read voltage) is adjusted") to determine data states of memory cells on the boundary word line (para. 17; "that determines (or estimates) the state of each neighbor memory cell of a selected memory cell before performing the read operation at the selected memory cell". It is noted that determining the data state of the target cell is the explicit reason the corrective read voltage is applied.");
applying a second corrective read voltage signal to a word line adjacent to the target word line during the corrective read operation (para. 61; "the control logic (e.g., the corrective reader 137) causes a first voltage (V.sub.H) to be applied to the first wordline WLn of the selected memory cell 510 and causes a second voltage (V.sub.L) to be applied to the wordlines adjacent to the first wordline") to determine data states of memory cells on the word line adjacent to the boundary word line (para. 16; "Thus, a corrective read operation can be performed to detect whether neighbor memory cells are erased or programmed.");
Tanaka does not disclose that the corrective read operation is an explicit result of error correcting code operations or the resulting applying of various pass voltages.
However, Peleato teaches in response to a bit error count of a read operation being above a threshold amount (pg. 3069, col. 2; "Typically, all post-read signal processing algorithms require re-reads using different thresholds", "finding optimal read thresholds in a dynamic manner to minimize BER and speed up the post-processing is essential". It is noted that Peleato's "re-read" is analogous to the "corrective read operation" of the instant application. Additionally, optimizing by minimizing bit error rate (BER) indicates that the re-read post processing is due to bit errors exceeding a threshold);
Tanaka as modified by Peleato is silent with respect to first and second pass voltages.
However, Kim teaches applying a first pass voltage to a number of unprogrammed word lines of the partially programmed block during the corrective read operation (para. 9; "a second pass voltage lower than the first pass voltage is applied to word lines coupled to non-programmed pages among the pages that are not selected for the read operation");
and applying a second pass voltage to a first number of programmed word lines of the partially programmed block that are nonadjacent to the target word line during the corrective read operation. (para. 9; "a first pass voltage is applied to word lines coupled to the programmed pages among pages that are not selected for the read operation"),
wherein the first pass voltage has a lower magnitude than the second pass voltage (para. 9; “a second pass voltage lower than the first pass voltage is applied").
Tanaka, Peleato, and Kim are from the same field of endeavor as applicant’s invention directed to performing memory read operations on non-volatile memory arrays. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the teachings of Tanaka’s corrective read based on the teachings of Peleato's BER reduction and along with Kim’s two level pass voltage to perform read operations on partially programmed blocks. Doing so would reduce the number of read retries required for read errors speeding up the memory device.
Regarding claim 16, Tanaka, Kim and Peleato combined disclose the limitations of claim 15
As applied, Kim further discloses wherein a magnitude of the first pass voltage is less than a magnitude of the second pass voltage (para. 9; "a second pass voltage lower than the first pass voltage is applied to word lines coupled to non-programmed pages among the pages that are not selected for the read operation". As noted previously, while Kim's first and second pass voltage nomenclature is reversed from that of the instant application, the magnitude relationship is the same).
Regarding claim 17, Tanaka, Kim and Peleato combined disclose the limitations of claim 15.
As applied, Tanaka further discloses the method of wherein a magnitude of the first corrective read voltage signal is lowered in response to the target word line being a boundary word line (abstr. "a corrective read operation to be performed at a selected memory cell. The operations include: causing a first voltage to be applied to a first wordline associated with the selected memory cell; causing a second voltage, having a lower magnitude than the first voltage, to be applied to wordlines adjacent to the first wordline").
Regarding claim 18, notwithstanding the rejection for indefiniteness above, Tanaka, Kim and Peleato combined disclose the limitations of claim 15.
As applied, Kim further discloses wherein the partially programmed block comprises a number of programmed word lines that include the number of inner word lines and a boundary word line (Fig. 6 where it illustrates the programmed word line group GR_P, with a boundary wordline (WL2) and inner wordlines (WL1, WL0))
and wherein the partially programmed block comprises the number of unprogrammed word lines (Fig. 6 where it illustrates the unprogrammed word line group GR_E)
and wherein a first unprogrammed word line of the number of unprogrammed word lines is adjacent to the boundary word line (Fig. 6 where it illustrates the first unprogrammed word line (WL3) is adjacent to the boundary wordline (WL2)).
Regarding claim 19, Tanaka, Kim and Peleato combined disclose the limitations of claim 15.
As applied, Tanaka further discloses further including applying the second corrective read voltage signal to the word line adjacent to the target word line during a 1 bit corrective read operation (para. 61; "the control logic (e.g., the corrective reader 137) causes a first voltage (V.sub.H) to be applied to the first wordline WLn of the selected memory cell 510 and causes a second voltage (V.sub.L) to be applied to the wordlines adjacent to the first wordline". See also para. 30; "Each of the memory devices 130 can include one or more arrays of memory cells. One type of memory cell, for example, single level cells (SLC) can store one bit per cell". It is noted that the instant application discloses that a 1 bit corrective read is associated with SLC memory cells).
Regarding claim 20, Tanaka, Kim and Peleato combined disclose the limitations of claim 15.
As applied, Tanaka further discloses further including applying a third corrective read voltage signal to another word line adjacent to the target word line during a 2 sided-2 bit corrective read operation (para. 61; "the control logic (e.g., the corrective reader 137) causes a first voltage (V.sub.H) to be applied to the first wordline WLn of the selected memory cell 510 and causes a second voltage (V.sub.L) to be applied to the wordlines adjacent to the first wordline". See also para. 30; "Each of the memory devices 130 can include one or more arrays of memory cells.", "In some embodiments, a particular memory device can include an SLC portion, and an MLC portion. It is noted that the instant application discloses that a 2 bit corrective read is associated with MLC memory cells. See also Fig. 5A & 5B where it illustrates corrective read voltages applied to word lines on both adjacent sides (e.g.: 2 sided) of the target word line WLn).
Response to Arguments
Applicant's arguments have been fully considered but they are not persuasive. Applicant contends that the obviousness rejections for the independent claims are improper because the previously applied references fail to teach or suggest all the limitations in the currently amended independent claims. Applicant notes three principal contentions regarding the references:
Applicant asserts that "Kim appears to teach applying pass voltages, but those pass voltages are not applied during a corrective read operation. The assertion fails to overcome the rejection because Tanaka already discloses the corrective-read framework, including the application of differentiated voltages to a target word line and to adjacent word lines in order to determine data states. Kim is relied upon solely for the known technique of applying differential pass voltages during a read operation on a partially programmed block. The rejection is based on a combination of references, not on any single reference. Applicant's argument attacks the references individually rather than the combination as a whole and is therefore unpersuasive.
Applicant further argues that the references fail to teach performing the corrective read operation "in response to a bit error count of a read operation being above a threshold amount." This limitation was previously present in only certain dependent claims and has now been elevated into the independent claims 1, 9 and 15. As set forth in the rejections above, Peleato expressly teaches performing additional / adaptive reads when an initial read produces a bit error rate too high for successful decoding.
Applicant's characterization of Peleato as merely teaching "an algorithm that uses a limited number of re-reads to characterize the noise distribution" is incomplete. Peleato specifically links BER / failed decoding to the performance of additional reads with different thresholds. This teaching is directly applicable to the newly independent BER-trigger limitation and, when combined with Tanaka and Kim, renders the claimed subject matter obvious.
For at least these reasons, the rejections of all claims are maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to James S. Wells whose telephone number is (703)756-1413. The examiner can normally be reached M-F 8:30-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Alexander Sofocleous can be reached at (571)272-0635. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/James S. Wells/Examiner, Art Unit 2825
/Alfredo Bermudez Lozada/Primary Examiner, Art Unit 2825
Prosecution Insights