DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This office action is in response to application filed on 06/17/2024.
Currently claims 1-20 are pending in the application.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/17/2024 was filed before the mailing date of the office action. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement was considered by the examiner.
Claim Rejections - 35 USC § 112 (b)
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION - The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
Claim 16 is rejected under 35 U.S.C. 112 (b), as being indefinite for failing to particularly pointing out and distinctly claim the subject matter which the inventor or a joint inventor, regard as their invention.
Claim 15 recites, “a first direction, the first direction perpendicular to a lower surface of the second substrate.” Claim 16, which depends from claim 15, again recites, “a first direction and a second direction, the first direction being parallel to an upper surface of the first substrate.” The term “first direction” is thereby given two mutually exclusive definitions within the same claim (perpendicular to the lower surface of the second substrate versus parallel to the upper surface of the first substrate, the substrates being stacked over one another), and it is unclear whether claim 16 refers back to the first direction of claim 15 or introduces a new, different direction. One of ordinary skill in the art therefore cannot ascertain the metes and bounds of the claim.
For purposes of examination, the “first direction” and “second direction” of claim 16 are interpreted as two intersecting horizontal directions parallel to the upper surface of the first substrate, distinct from the first direction of claim 15. Applicant is required to amend claim 16 to resolve the conflict (e.g., “a second direction and a third direction”).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-9 and 11-13 are rejected under 35 U.S.C. 103 as unpatentable over US 2021/0296324 A1 (Lim) and further in view of US 2022/0223524 A1 (Choi).
Regarding claim 1, Lim teaches, a memory device (vertical memory device; Lim Fig. 12; [0109]) comprising:
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a lower interconnection structure (102, 104a, 104b, 106a, 106b, 108a, 108b; circuit patterns; Lim Fig. 12; [0023]) on a substrate (100; substrate; Lim Fig. 12; [0021] - [0022]), the lower interconnection structure including a plurality of circuit components (102; lower transistors; Lim Fig. 12; [0023]) and a plurality of lower conductive patterns (104b, 106b, 108b; lower conductive patterns; Lim Fig. 12; [0023]–[0025]);
a cell stack structure (182; cell stack structure; Lim Fig. 12; [0034]) on the lower interconnection structure (102, 104a–108b; circuit patterns; Lim Fig. 12; [0023]), the cell stack structure including a plurality of gate electrodes (180; gate electrodes; Lim Fig. 12; [0036]) stacked and spaced apart from each other in a vertical direction (vertical direction; Lim Fig. 1A; [0019], [0036]), the vertical direction perpendicular to an upper surface of the substrate (100);
an interlayer insulating layer (178; first insulating interlayer; Lim Fig. 12; [0042]) covering the cell stack structure (182; cell stack structure; Lim Fig. 12; [0042]);
an upper interconnection structure (200, 206; second and third insulating interlayers with upper contacts and upper conductive patterns; Lim Fig. 12; [0062]–[0069], [0110]) on the interlayer insulating layer (178; first insulating interlayer; Lim Fig. 12; [0062]), the upper interconnection structure including a plurality of upper conductive patterns (202, 203, 204, 210, 212, 220, 222; cell upper contacts, upper dummy contact, peripheral upper contacts, and upper conductive patterns; Lim Fig. 12; [0063]–[0069], [0110]–[0111]);
one or more effective contact structures (194; through via contact; Lim Fig. 12; [0044]) respectively passing through the interlayer insulating layer (178; first insulating interlayer; Lim Fig. 12; [0044]), the one or more effective contact structures respectively having an upper surface and a lower surface, the upper surface of an effective contact structure being in contact with a first upper pad (204; first peripheral upper contact; Lim Fig. 12; [0063], [0111]) electrically connected to an external pad of the one or more external pads - Lim’s first peripheral upper contact 204 is electrically connected through the second peripheral upper contact (210; second peripheral upper contact; Lim Fig. 12; [0065]) to the first upper conductive pattern (220; first upper conductive pattern; Lim Fig. 12; [0069]–[0070]), and the external pad is taught by Choi below;
the lower surface of the effective contact structure (194) being in contact with a first lower pad (108b; third lower conductive pattern contacting the through via contact 194; Lim Fig. 12; [0027], [0044]) electrically connected to the plurality of circuit components (102; lower transistors; Lim Fig. 12; [0047]); and
one or more preliminary contact structures (196; dummy through via contacts; Lim Fig. 12; [0045], [0055]) respectively passing through the interlayer insulating layer (178; first insulating interlayer; Lim Fig. 12; [0045]), the one or more preliminary contact structures respectively having an upper surface and a lower surface, the upper surface of a preliminary contact structure being in contact with a second upper pad (203; upper dummy contact; Lim Fig. 12; [0110]–[0111]), and the lower surface of the preliminary contact structure being in contact with a second lower pad (108b; isolated third lower conductive pattern contacting the dummy through via contact 196; Lim Figs. 1A, 12; [0045]–[0046], [0048]), wherein the one or more preliminary contact structures are electrically floating (196; dummy through via contact, “electrically floated”; Lim Fig. 12; [0111]; see also [0048]).
But Lim does not expressly teach that the upper interconnection structure includes “one or more external pads,” with the first upper pad “electrically connected to an external pad of the one or more external pads.”
However, in analogous art, Choi teaches, a vertical memory device (1100; semiconductor device; Choi Fig. 24; [0097]) having a memory cell structure (1100S; second structure; Choi Fig. 24; [0097]) over a peripheral circuit structure (1110F; first structure; Choi Fig. 24; [0097]), in which “one or more external pads” (1101; input/output pads; Choi Fig. 24; [0101]), (2210; input/output pad; Choi Fig. 26; [0112], [0118]) are provided above the memory cell structure and are electrically connected, through connecting lines (1135; input/output connecting lines; Choi Fig. 24; [0101]), (3265; input/output connecting wiring; Choi Fig. 26; [0118]) extending from the memory cell structure to the peripheral circuit structure, to the peripheral circuits (1130; logic circuit; Choi Fig. 24; [0101]), (3110; peripheral wirings; Choi Fig. 26; [0118]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lim and Choi before him/her, because external input/output pads electrically connected to the peripheral circuits allow the memory device to communicate with, and receive signals from, an external controller (Choi [0101], [0112]–[0113]), and Lim’s through via contact 194 is provided precisely to transfer a voltage applied from the upper wiring 220 to the lower transistors 102 of the peripheral circuits (Lim [0070]). Absent this teaching in Lim, a person with ordinary skill in the art would be motivated to reach out to Choi while forming the vertical memory device of Lim.
Regarding claim 2, the combination of Lim and Choi teaches, the memory device of claim 1, wherein the one or more preliminary contact structures include a plurality of first preliminary contact structures (196; dummy through via contacts; Lim Figs. 2, 12; [0055]), and the plurality of first preliminary contact structures are adjacent to the one or more effective contact structures (194; through via contact; Lim Fig. 2; [0054]–[0055]), or the plurality of first preliminary contact structures are adjacent to each other (196; dummy through via contacts; Lim Fig. 2; [0057]).
Regarding claim 3, the combination of Lim and Choi teaches, the memory device of claim 2, wherein among the plurality of first preliminary contact structures (196; dummy through via contacts; Lim Fig. 2; [0055]) and the one or more effective contact structures (194; through via contact; Lim Fig. 2; [0055]), a plurality of contact structures that are adjacent to each other are spaced apart from each other by a distance (distance between through via contact 194 and dummy through via contact 196; Lim Fig. 2; [0058]), the distance being 10 times or less of a largest diameter (upper diameter; Lim Fig. 1A; [0050], [0058]) of a through-via hole (190, 192; through via hole, dummy through via hole; Lim Fig. 8; [0087], [0094]) in which the plurality of adjacent contact structures are formed.” Lim teaches a ratio of the upper diameter of the through via contact to the distance between the through via contact and the dummy through via contact of about 1:0.5 to 10, i.e., a distance of 0.5 to 10 times the upper diameter (Lim [0007], [0058]). Because each via has a sloping sidewall whose diameter decreases from top to bottom, the upper diameter is the largest diameter of the through-via hole (Lim [0050], [0094]). Lim’s range lies entirely within the claimed range of “10 times or less”; a range disclosed in the prior art that lies within a claimed range renders the claimed range obvious (MPEP 2144.05(I); see also MPEP 2131.03).
Regarding claim 4, the combination of Lim and Choi teaches, the memory device of claim 1, wherein the one or more effective contact structures (194; through via contact; Lim Fig. 2; [0056]) and the one or more preliminary contact structures (196; dummy through via contacts; Lim Fig. 2; [0056]) are arranged in a first direction (first direction; Lim Fig. 2; [0019], [0056]) and a second direction (second direction; Lim Fig. 2; [0019], [0056]), the first direction being parallel to the upper surface of the substrate (100; substrate; Lim Fig. 1A; [0019]), and the second direction being parallel to the upper surface of the substrate and intersecting the first direction (first and second horizontal directions, “two intersecting directions substantially parallel to the upper surface of the substrate; Lim Fig. 2; [0019]).
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Regarding claim 5, the combination of Lim and Choi teaches, the memory device of claim 4, wherein the first direction (first direction; Lim Fig. 2; [0019]) and the second direction (second direction; Lim Fig. 2; [0019]) are orthogonal to each other. Lim Fig. 2 depicts the first and second directions as perpendicular axes, with the through via contact 194 and the dummy through via contacts 196 laid out on a rectangular grid along those axes.
Regarding claim 6, the combination of Lim and Choi teaches, the memory device of claim 4, wherein the one or more effective contact structures (194; through via contact; Lim Fig. 2; [0056]–[0057]) and the one or more preliminary contact structures (196; dummy through via contacts; Lim Fig. 2; [0056]–[0057]) are arranged at a predetermined first interval in the first direction (spacing in first direction; Lim Fig. 2; [0057]), and are arranged at a predetermined second interval in the second direction (spacing in second direction; Lim Fig. 2; [0057]). Lim’s Fig. 2 shows the contacts 194/196 on a regular array with a fixed pitch along each direction.
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Regarding claim 7, the combination of Lim and Choi teaches, the memory device of claim 6, wherein the first interval and the second interval are the same (distance between the through via contact 194 and the dummy through via contacts 196 and distance between the dummy through via contacts 196 “may be substantially the same; Lim Fig. 2; [0057]).
Regarding claim 8, the combination of Lim and Choi teaches, the memory device of claim 1, wherein the one or more preliminary contact structures include a plurality of second preliminary contact structures (196a; dummy through via contacts; Lim Figs. 17–18; [0136]–[0137]), the plurality of second preliminary contact structures sharing … one second lower pad (130a; pad semiconductor pattern, contacted by “a plurality of dummy through via contacts 196a”; Lim Fig. 17; [0134], [0137]),” the dummy through via contacts 196a being electrically isolated from the peripheral circuits (Lim [0142]). Lim further teaches a second upper pad on the dummy contact (203; upper dummy contact; Lim Fig. 12; [0110]–[0111]), and teaches that a plurality of through via contacts may share one upper pad (204; first peripheral upper contact, contacting “a plurality of through via contacts 198”; Lim Fig. 16; [0129]) and one lower pad (108b; third lower conductive pattern; Lim Fig. 16; [0127]), and that one upper connection pattern may contact the upper surfaces of several contacts (204a; upper connection pattern; Lim Fig. 14; [0116]).
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But Lim does not expressly show the plurality of dummy through via contacts 196a also sharing “one second upper pad.”
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lim before him/her, (1) because Lim presents one-pad-per-via and shared-pad configurations as interchangeable alternatives for both upper and lower pads (Lim [0127], [0129], [0137]), and a single shared pad over the dummy region simplifies the wiring layout where Lim seeks design freedom (Lim [0068], [0143]); (2) since the modification amounts to making integral the individual upper dummy contacts 203 into one shared upper dummy pad, in the same manner Lim already shares the lower pad 130a (MPEP 2144.04(V)(B)); and (3) with a reasonable expectation of success, yielding the predictable result of a plurality of dummy through via contacts sharing one upper pad and one lower pad that remain electrically floating, because neither the upper dummy contact 203 nor the pad semiconductor pattern 130a is connected to any circuit (Lim [0111], [0142]).
Regarding claim 9, the combination of Lim and Choi teaches, the memory device of claim 8, wherein the plurality of second preliminary contact structures (196a; dummy through via contacts; Lim Figs. 17–18; [0137], [0139]) are adjacent to each other.
Regarding claim 11, the combination of Lim and Choi teaches, the memory device of claim 1, wherein the one or more effective contact structures (194; through via contact; Lim Fig. 1A; [0049]–[0050], [0059]) and the one or more preliminary contact structures (196; dummy through via contact; Lim Fig. 1A; [0049]–[0050], [0059]) have the same shape - the heights are substantially the same ([0049]), each has a sloping sidewall ([0050]), and the upper diameters are substantially the same ([0059]).
Regarding claim 12, the combination of Lim and Choi teaches, the memory device of claim 1, wherein each contact structure of the one or more effective contact structures (194; through via contact filling through via hole 190; Lim Fig. 9; [0099]) and the one or more preliminary contact structures (196; dummy through via contacts filling dummy through via holes 192; Lim Fig. 9; [0099]) includes a through-hole via (190, 192; through via hole, dummy through via hole; Lim Fig. 8; [0087]).
Regarding claim 13, the combination of Lim and Choi teaches, the memory device of claim 1, wherein the first upper pad (204; first peripheral upper contact; Lim Fig. 12; [0110]) and the second upper pad (203; upper dummy contact; Lim Fig. 12; [0110]) are included in a lowermost conductive pattern among the plurality of upper conductive patterns (conductive patterns passing through second insulating interlayer 200, the lowermost level of the upper wiring; Lim Fig. 12; [0110]), and the first lower pad and the second lower pad (108b; third lower conductive patterns; Lim Fig. 12; [0027]) are included in an uppermost conductive pattern among the plurality of lower conductive patterns (108b; third lower conductive patterns “disposed at an uppermost portion among lower wirings”; Lim Fig. 12; [0026]).
Claim 10 is rejected under 35 U.S.C. 103 as unpatentable over Lim in view of Choi, and further in view of US 2021/0375901 A1 (Oh).
Regarding claim 10, the combination of Lim and Choi teaches the memory device of claim 1, wherein the one or more effective contact structures include a plurality of first effective contact structures (198; through via contacts; Lim Fig. 16; [0126]), the plurality of first effective contact structures sharing one first upper pad (204; first peripheral upper contact, contacting “a plurality of through via contacts 198”; Lim Fig. 16; [0129]) and one first lower pad (108b; third lower conductive pattern contacted by the plurality of through via contacts 198; Lim Fig. 16; [0127]–[0128]), and Choi teaches external pads (1101; input/output pads; Choi Fig. 24; [0101]).
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But neither Lim nor Choi expressly teaches that the first effective contact structures “are electrically connected to a power pad of the one or more external pads.”
However, in analogous art, Oh teaches a vertical memory device having external coupling pads (130; external coupling pads; Oh Fig. 13; [0067], [0150]), including “a power pad” (130; “external coupling pad for a ground voltage VSS”; Oh Fig. 13; [0150]), and teaches that the large current carried on the ground/source path causes a resistance-induced potential rise (source line bouncing) that degrades sensing (Oh [0153]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lim, Choi and Oh before him/her, because power-supply paths carry large currents whose resistance must be minimized (Oh [0153]), and Lim teaches that a plurality of parallel through via contacts 198 sharing one upper pad and one lower pad increases the electrical path and keeps the connection intact even if individual vias are defective (Lim [0130]). Absent this teaching in Lim and Choi, a person with ordinary skill in the art would be motivated to reach out to Oh while forming the vertical memory device of Lim and Choi.
Claim 14 is rejected under 35 U.S.C. 103 as unpatentable over US 2021/0296324 A1 (Lim) and further in view of US 2022/0223524 A1 (Choi).
Regarding claim 14, Lim teaches, a memory device (vertical memory device; Lim Fig. 12; [0109]) comprising:
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a lower interconnection structure (102, 104a, 104b, 106a, 106b, 108a, 108b; circuit patterns; Lim Fig. 12; [0023]) on a substrate (100; substrate; Lim Fig. 12; [0021] - [0022]), the lower interconnection structure including a plurality of circuit components (102; lower transistors; Lim Fig. 12; [0023]) and a plurality of lower conductive patterns (104b, 106b, 108b; lower conductive patterns; Lim Fig. 12; [0023]–[0025]);
a cell stack structure (182; cell stack structure; Lim Fig. 12; [0034]) on the lower interconnection structure (102, 104a–108b; circuit patterns; Lim Fig. 12; [0023]), the cell stack structure including a plurality of gate electrodes (180; gate electrodes; Lim Fig. 12; [0036]) stacked and spaced apart from each other in a vertical direction (vertical direction; Lim Fig. 1A; [0019], [0036]), the vertical direction perpendicular to an upper surface of the substrate (100);
an interlayer insulating layer (178; first insulating interlayer; Lim Fig. 12; [0042]) covering the cell stack structure (182; cell stack structure; Lim Fig. 12; [0042]);
an upper interconnection structure (200, 206; second and third insulating interlayers with upper contacts and upper conductive patterns; Lim Fig. 12; [0062]–[0069], [0110]) on the interlayer insulating layer (178; first insulating interlayer; Lim Fig. 12; [0062]), the upper interconnection structure including a plurality of upper conductive patterns (202, 203, 204, 210, 212, 220, 222; cell upper contacts, upper dummy contact, peripheral upper contacts, and upper conductive patterns; Lim Fig. 12; [0063]–[0069], [0110]–[0111]);
an effective contact structures (194; through via contact; Lim Fig. 12; [0044]) passing through the interlayer insulating layer (178; first insulating interlayer; Lim Fig. 12; [0044]), the effective contact structures having an upper surface and a lower surface, the upper surface of an effective contact structure being in contact with a first upper pad (204; first peripheral upper contact; Lim Fig. 12; [0063], [0111]) electrically connected to an external pad of the one or more external pads - Lim’s first peripheral upper contact 204 is electrically connected through the second peripheral upper contact (210; second peripheral upper contact; Lim Fig. 12; [0065]) to the first upper conductive pattern (220; first upper conductive pattern; Lim Fig. 12; [0069]–[0070]), and the external pad is taught by Choi below;
the lower surface of the effective contact structure (194) being in contact with a first lower pad (108b; third lower conductive pattern contacting the through via contact 194; Lim Fig. 12; [0027], [0044]) electrically connected to the plurality of circuit components (102; lower transistors; Lim Fig. 12; [0047]); and
one or more preliminary contact structures (196; dummy through via contacts; Lim Fig. 12; [0045], [0055]) respectively passing through the interlayer insulating layer (178; first insulating interlayer; Lim Fig. 12; [0045]), the one or more preliminary contact structures respectively having a structure same as the effective contact structure (194/196; same height, same upper diameter, same barrier pattern and metal pattern; Lim Fig. 1A; [0049], [0059], [0061], [0099]), wherein the one or more preliminary contact structures are electrically floating (196; dummy through via contact, “electrically floated”; Lim Fig. 12; [0111]).
But Lim does not expressly teach that the upper interconnection structure includes “one or more external pads,” with the first upper pad “electrically connected to an external pad of the one or more external pads.”
However, in analogous art, Choi teaches, a vertical memory device (1100; semiconductor device; Choi Fig. 24; [0097]) having a memory cell structure (1100S; second structure; Choi Fig. 24; [0097]) over a peripheral circuit structure (1110F; first structure; Choi Fig. 24; [0097]), in which “one or more external pads” (1101; input/output pads; Choi Fig. 24; [0101]), (2210; input/output pad; Choi Fig. 26; [0112], [0118]) are provided above the memory cell structure and are electrically connected, through connecting lines (1135; input/output connecting lines; Choi Fig. 24; [0101]), (3265; input/output connecting wiring; Choi Fig. 26; [0118]) extending from the memory cell structure to the peripheral circuit structure, to the peripheral circuits (1130; logic circuit; Choi Fig. 24; [0101]), (3110; peripheral wirings; Choi Fig. 26; [0118]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Lim and Choi before him/her, because external input/output pads electrically connected to the peripheral circuits allow the memory device to communicate with, and receive signals from, an external controller (Choi [0101], [0112]–[0113]), and Lim’s through via contact 194 is provided precisely to transfer a voltage applied from the upper wiring 220 to the lower transistors 102 of the peripheral circuits (Lim [0070]). Absent this teaching in Lim, a person with ordinary skill in the art would be motivated to reach out to Choi while forming the vertical memory device of Lim.
Claims 15-20 are rejected under 35 U.S.C. 103 as unpatentable over US 2022/0068857 A1 (Chen) in view of US 2021/0296324 A1 (Lim).
Regarding claim 15, Chen teaches, a memory device (100; 3D-NAND memory device; Chen Fig. 1; [0037]) comprising: a lower chip (100B; transistor structure (periphery structure); Chen Fig. 1; [0037], [0048]) including a first substrate (160; periphery substrate; Chen Fig. 1; [0048]), a plurality of circuit components (162; transistors; Chen Fig. 1; [0048]) on the first substrate, and a lower interconnection structure (158, 154, 152; inter-layer dielectric, contact structures, second bonding structures; Chen Fig. 1; [0048]) electrically connected to the plurality of circuit components (162; transistors; Chen Fig. 1; [0048]);
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an upper chip (100A, 100C; memory cell structure and connection structure; Chen Fig. 1; [0037], [0049]) on the lower chip, the upper chip including a second substrate (102; base layer, which may be single crystal silicon or an SOI structure; Chen Fig. 1; [0037]–[0038]), an upper interconnection structure (104, 106; first dielectric layer and connection structures; Chen Fig. 1; [0047]) on an upper surface (102”; second side of base layer; Chen Fig. 1; [0047]) of the second substrate, an external pad (106d; connection structure coupled to bonding pad contacts 144 that function as input/output pins (DQ pads); Chen Figs. 1, 3B; [0045], [0047], [0053]) connected to the upper interconnection structure (106; connection structures; Chen Fig. 1; [0060]),
a cell stack structure (110; memory cell stack; Chen Fig. 1; [0038]) including a plurality of gate electrodes (116; word line layers; Chen Fig. 1; [0038]) stacked and spaced apart from each other in a first direction (Z; vertical direction; Chen Fig. 1; [0039]), the first direction perpendicular to a lower surface (102’; first side of base layer; Chen Fig. 1; [0037]–[0038]) of the second substrate,
an interlayer insulating layer (109; third dielectric layer; Chen Fig. 1; [0043]) surrounding a lower surface and a side surface of the cell stack structure (110; memory cell stack; Chen Fig. 1; [0043]),
an intermediate interconnection structure (156, 148, 150; first dielectric stack, first vias, first bonding structures; Chen Fig. 1; [0046]) below the interlayer insulating layer and bonded to the lower interconnection structure (150 bonded to 152; first and second bonding structures; Chen Figs. 1, 5; [0049], [0056]),
one or more effective contact structures (144; bonding pad contacts; Chen Fig. 1; [0045]) respectively passing through the interlayer insulating layer (108, 109; second and third dielectric layers; Chen Fig. 1; [0045]),
the one or more effective contact structures respectively having an upper surface and a lower surface, the upper surface of an effective contact structure being in contact with a first upper pad (106d; portion of connection structure extending through the first dielectric layer 104 onto the bonding pad contact 144; Chen Figs. 1, 7–8; [0047], [0058], [0060]) electrically connected to the external pad (106d; Chen Fig. 1; [0045], [0047]), the lower surface of the effective contact structure being in contact with a first lower pad (148; first via; Chen Fig. 1; [0046]) electrically connected to the circuit components (144 coupled to contact structures 154 through 152, 150 and 148; Chen Fig. 1; [0049]; 154 coupled to transistors 162; [0048]),
But Chen does not expressly teach, one or more preliminary contact structures respectively passing through the interlayer insulating layer … the one or more preliminary contact structures respectively having an upper surface and a lower surface, the upper surface of a preliminary contact structure being in contact with a second upper pad, and the lower surface of the preliminary contact structure being in contact with a second lower pad, wherein the one or more preliminary contact structures are electrically floating.
However, in analogous art, Lim teaches, one or more preliminary contact structures (196; dummy through via contacts; Lim Fig. 12; [0045], [0055]) passing through the interlayer insulating layer (178; first insulating interlayer; Lim Fig. 12; [0045]) adjacent to an effective through via contact (194; through via contact; Lim Fig. 12; [0044], [0054]), each having “an upper surface … in contact with a second upper pad” (203; upper dummy contact; Lim Fig. 12; [0110]–[0111]) and “a lower surface … in contact with a second lower pad” (108b; isolated third lower conductive pattern; Lim Figs. 1A, 12; [0046], [0048]), “wherein the one or more preliminary contact structures are electrically floating” (196; “electrically floated”; Lim Fig. 12; [0111]), the dummy contacts being formed together with the through via contact to reduce photolithography difficulty and not-open defects of deep through vias (Lim [0089] - [0090], [0097] - [0098]).
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Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chen and Lim before him/her, because Chen’s bonding pad contacts 144 are deep through-contacts extending the full thickness of the second and third dielectric layers 108/109 alongside the memory cell stack (Chen Fig. 1; [0045]), and Lim teaches that isolated deep through vias suffer patterning difficulty and not-open defects that are reduced by forming adjacent, electrically floating dummy through vias landing on isolated pads (Lim [0089] - [0090], [0097] - [0098], [0111]). Absent this teaching in Chen, a person with ordinary skill in the art would be motivated to reach out to Lim while forming the 3D-NAND memory device of Chen.
Regarding claim 16, as best understood (see the 112(b) rejection above), the combination of Chen and Lim teaches, the memory device of claim 15, where Chen teaches the first substrate having an upper surface (160’; first side of periphery substrate, lying in the X-Y plane; Chen Fig. 1; [0048]) and Lim teaches “wherein the one or more effective contact structures (194; through via contact; Lim Fig. 2; [0056]) and the one or more preliminary contact structures (196; dummy through via contacts; Lim Fig. 2; [0056]) are arranged in a first direction (first direction; Lim Fig. 2; [0019]) and a second direction (second direction; Lim Fig. 2; [0019]), the first direction being parallel to an upper surface of the first substrate, and the second direction being parallel to the upper surface of the first substrate and intersecting the first direction (first and second horizontal directions parallel to the substrate upper surface; Lim Fig. 2; [0019], [0056]).
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Regarding claim 17, the combination of Chen and Lim teaches, the memory device of claim 15, where Chen teaches a plurality of contacts sharing one upper pad (144, 106d; two bonding pad contacts both contacting one connection structure 106d; Chen Fig. 1; [0047]), and Lim teaches “wherein the one or more preliminary contact structures include a plurality of second preliminary contact structures (196a; dummy through via contacts; Lim Figs. 17–18; [0136]–[0137]), the plurality of second preliminary contact structures sharing … one second lower pad (130a; pad semiconductor pattern contacted by a plurality of dummy through via contacts 196a; Lim Fig. 17; [0134], [0137]),” as well as a plurality of contacts sharing one upper pad and one lower pad (198, 204, 108b; through via contacts, first peripheral upper contact, third lower conductive pattern; Lim Fig. 16; [0127], [0129]).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chen and Lim before him/her, because both Chen (Fig. 1; [0047]) and Lim ([0127], [0129], [0137]) present a single pad shared by several vertical contacts as an ordinary layout alternative, which reduces the number of discrete pads over the dummy region. Absent this teaching in Chen, a person with ordinary skill in the art would be motivated to reach out to Lim while forming the 3D-NAND memory device of Chen.
Regarding claim 18, the combination of Chen and Lim teaches, the memory device of claim 15, wherein the first upper pad (106d; connection structure; Chen Fig. 1; [0047], [0060]) … [is] included in conductive patterns of a lowermost layer of the upper interconnection structure (106; connection structures formed from the single conductive layer over the first dielectric layer 104; Chen Figs. 1, 8; [0060]), and the first lower pad (148; first via; Chen Fig. 1; [0046]) … [is] included in conductive patterns of an uppermost layer of the intermediate interconnection structure (148; first vias, the layer of the first dielectric stack 156 adjacent to the third dielectric layer 109; Chen Fig. 1; [0046], [0054]), and Lim teaches forming the second upper pad in the same wiring level as the first upper pad (203, 204; upper dummy contact and first peripheral upper contact, both passing through the second insulating interlayer 200; Lim Fig. 12; [0110]) and the second lower pad in the same wiring level as the first lower pad (108b; third lower conductive patterns; Lim Figs. 1A, 12; [0045] - [0046]). In the combination, the second upper pad and the second lower pad are therefore formed in the same layers as Chen’s first upper pad and first lower pad, respectively.
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Regarding claim 19, the combination of Chen and Lim teaches, the memory device of claim 15, where Chen teaches that the bonding pad contacts (144; bonding pad contacts; Chen Fig. 2; [0051]) are formed through the second and third dielectric layers from the top surface (109’; top surface of third dielectric layer; Chen Fig. 1; [0045]) over the cell array substrate before bonding, the top surface 109’ then facing the first substrate after bonding (160’; first side of periphery substrate; Chen Fig. 5; [0056]), and Lim teaches through via contacts and dummy through via contacts each having a sloping sidewall whose diameter gradually decreases away from the surface from which the hole is etched (194, 196; through via contact, dummy through via contact; Lim Fig. 1A; [0050], [0094]). In the combination, the effective and preliminary contact structures are widest at the top surface 109’ adjacent the first substrate, i.e., “the one or more effective contact structures and the one or more preliminary contact structures have a diameter gradually decreasing in a direction from the first substrate to the second substrate.”
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Chen and Lim before him/her, because a deep, high-aspect-ratio contact hole etched from one surface inherently tapers toward its bottom (Lim [0050], [0094]–[0097]). Absent this teaching in Chen, a person with ordinary skill in the art would be motivated to reach out to Lim while forming the 3D-NAND memory device of Chen.
Regarding claim 20, the combination of Chen and Lim teaches, the memory device of claim 15, wherein the one or more effective contact structures (144; bonding pad contacts; Chen Fig. 1; [0045]) … pass through the interlayer insulating layer (108; second dielectric layer “arranged in the base layer 102”; Chen Fig. 1; [0043], [0045], [0051]) around the second substrate (102; base layer; Chen Fig. 1; [0043]),” and Lim teaches the preliminary contact structures formed adjacent to and through the same insulating layer as the effective contact (196; dummy through via contacts; Lim Fig. 2; [0045], [0055]). In the combination, the preliminary contact structures likewise pass through the interlayer insulating layer around the second substrate.
Examiner’s Note (Additional Prior Arts)
The examiner included a few prior arts which were not used in the rejection but are relevant to the disclosure.
US 2022/0045045 A1 (Lee1) – A semiconductor memory device is disclosed includeing a peripheral circuit layer; a bonding structure disposed on the peripheral circuit layer; a channel structure disposed on the bonding structure; a first gate contact structure including a first vertical part penetrating the bonding structure and a first horizontal part intersecting with the first vertical part and extending from the first vertical part; and a first gate conductive pattern in contact with a side all of the first horizontal part, the first gate conductive pattern being spaced apart from the first vertical part, the first gate conductive pattern extending to surround the channel structure.
US 2022/0093637 A1 (Lee2) – A memory device is disclosed including a peripheral circuit layer including a plurality of conductive pads; a bonding structure disposed on the peripheral circuit layer; a cell stack structure disposed on the bonding structure, the cell stack structure including a plurality of gate conductive patterns; and a plurality of vertical gate contact structures respectively connecting the plurality of conductive pads and the plurality of gate conductive patterns while penetrating the bonding structure, wherein each of the plurality of gate conductive patterns includes a first horizontal part and a second horizontal part, which extend horizontally from a cell region to a contact region, and a third horizontal part connected to one end of the first horizontal part and one end of the second horizontal part, the third horizontal part being connected to a corresponding gate contact structurek.
US 2021/0090994 A1 (Noh) – A contact plug penetrating a stack structure in a contact region to a contact pad at the bottom of the stack, with oxide support structures in the contact region.
US 2019/0312051 A1 (Park) - A semiconductor memory device is disclosed comprising a peripheral circuit structure on a first substrate, a second substrate on the peripheral circuit structure, a stack structure on the second substrate and comprising a plurality of gate electrodes, a through dielectric pattern penetrating the stack structure and the second substrate, and a vertical supporter on a top surface of the second substrate and vertically extending from the top surface of the second substrate and penetrating the stack structure and the through dielectric pattern.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to S M SOHEL IMTIAZ whose telephone number is (408) 918-7566. The examiner can normally be reached on 8AM-5PM, M-F, PST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8458. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/S M SOHEL IMTIAZ/Primary Patent Examiner
Art Unit 2812
10/11/2026
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