DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 07/23/2026 Amendment and RCE.
Claims 1-5, 7-11, 13-18, 20 are pending and examined. Claims 6, 12 and 19 have been cancelled.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-11, 13-18, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 11,728,003 to Suh et al. (hereafter Suh).
Regarding independent claim 1, Suh teaches a system comprising:
a controller including an error correction circuit (FIG. 3: a system ECC decoder 131 and a system ECC encoder 132), wherein the controller is configured to provide a plurality of data bits and the error correction circuit is configured to provide a plurality of module parity bits based on the plurality of data bit as part of a write operation (see 9:58-10:6); and
a memory module comprising:
a plurality of memory devices (FIG. 1: memories 150-1 to 150-4), each memory device of the plurality configured to store a portion of the plurality of data bits and further store a portion of the plurality of module parity bits (FIG. 3: storing data in portion 932 and system ECCs in portion 934).
Regarding dependent claim 2, Suh teaches wherein the memory module comprises: a plurality of channels, each associated with one of the plurality of memory devices (see FIG. 1), each of the plurality of channels comprising a plurality of data terminals, wherein a first set of the plurality of data terminals is configured to receive the portion of the plurality of data bits (FIG. 3: terminals DQ[0:7] for data) and an additional one of the plurality of data terminals is configured to receive the portion of the plurality of module parity bits as part of the write operation (FIG. 3: terminal DM for parity bits in write operation, see 7:60-8:3).
Regarding dependent claim 3, Suh teaches wherein the plurality of memory devices each include a mode register (FIG. 3: mode register 179) configured to put the memory module in a first mode or a second mode, wherein in the first mode there are a first number of the plurality of module parity bits and in the second mode there are a second number of the plurality of module parity bits (see FIG. 9).
Regarding dependent claim 4, Suh teaches wherein the first number of the plurality of module parity bits enables the error correction circuit to perform a first level of error correction and wherein the second number of the plurality of module parity bits enables the error correction circuit to perform a second level of error correction (FIG. 9: e.g. mode 0010B and mode 0011B perform ECC parity [0:23] and ECC parity [0:15], respectively).
Regarding dependent claim 5, Suh teaches wherein the controller configured to provide a plurality of metadata bits as part of the write operation, and wherein the error correction circuit is configured to generate the plurality of module parity bits based on the plurality of data bits and the plurality of metadata bits (FIG. 21: metadata stored in portion 934, see 20:5-23).
Regarding dependent claim 6, Suh teaches wherein the memory module is configured to operate in an 8x2p3 mode (the mode is regarding how data and module parity are stored in the memory array, see FIGS. 17-18 as how data and parity are stored).
Regarding independent claim 8, Suh teaches an apparatus comprising:
a module settings register (FIG. 3: mode register 179) configured to set the apparatus in a first mode or a second mode (FIG. 9: e.g. mode 0010B and mode 0011B perform ECC parity [0:23] and ECC parity [0:15], respectively);
a plurality of memory devices (FIG. 1: memories 150-1 to 150-4), each memory device of the plurality configured to receive and store both a portion of a plurality of data bits and a portion of a plurality of module parity bits (FIG. 3: storing data in portion 932 and system ECCs in portion 934), wherein the plurality of module parity bits is a first number of module parity bits in the first mode or a second number of module parity bits in the second mode; and
a plurality of pseudo-channels, each associated with one of the plurality of memory devices, each of the plurality of pseudo-channels including a first set of data terminals configured to transmit the associated portion of the plurality of data bits and an additional data terminal configured to transmit the associated portion of the plurality of module parity bits (FIG. 3: comprising DQ[0:7] for data and DM for parity bits in write operation, see 7:60-8:3).
Regarding dependent claim 9, Suh teaches wherein each of the plurality of memory devices has a first capacity in the first mode or a second capacity in the second mode (FIG. 9: higher ECC parity bits mean lower data capacity and vice versa).
Regarding dependent claim 10, Suh teaches wherein each of the plurality of memory devices includes an error correction circuit configured to generate a plurality of parity bits based on the stored portion of the plurality of data bits and the stored portion of the plurality of module parity bits (FIG. 3: a system ECC decoder 131 and a system ECC encoder 132).
Regarding dependent claim 11, Suh teaches wherein the first number of module parity bits enables a first level of correction of the plurality of data bits and the second number of module parity bits enables a second level of correction of the plurality of data bits (FIG. 9: e.g. mode 0010B and mode 0011B perform ECC parity [0:23] and ECC parity [0:15], respectively).
Regarding dependent claim 13, Suh teaches wherein the module settings register is configured to implicitly allow a user to select the first mode or the second mode (FIG. 3: user is allowed to set the mode register 179 via host, see 22:63-23:6).
Regarding dependent claim 14, Suh teaches wherein a number of bits of the plurality of data bits is the same in the first mode and the second mode (when the data and parity data are stored in separated rows as shown in FIG. 18, number of bits read corresponding to a row address in each of the modes of FIG. 9 would be the same).
Regarding independent claim 15, Suh teaches a method comprising:
selecting a first mode or a second mode for a memory module (FIG. 9: e.g. mode 0010B and mode 0011B perform ECC parity [0:23] and ECC parity [0:15], respectively);
selecting a first portion or a second portion of a word line in each of the plurality of memory devices (FIG. 3: data portion 932 and system ECC portion 934; FIG. 17 shows data portion and system ECC portion are stored on the same word line);
storing a respective portion of a plurality of data bits along the selected one of the first portion or the second portion of the word line and further storing a respective portion of a plurality of module parity bits along the non-selected one of the first portion or the second portion of the word line on each of a plurality of memory devices of the memory module (see FIG. 17), wherein the plurality of module parity bits is a first number of bits in the first mode and a second number of bits in the second mode (i.e. parity bits corresponding to ECC mode).
Regarding dependent claim 16, Suh teaches wherein the first number of module parity bits enables correction of a first number of the plurality of data bits and wherein the second number of module parity bits enables correction of a second number of the plurality of data bits (because they are ECC parity bits).
Regarding dependent claim 17, Suh teaches reading the plurality of data bits and the plurality of module parity bits over a plurality of channels, each associated with one of the plurality of memory devices, wherein respective portion of the plurality of data bits is read over a first and a second data terminal of the channel (FIG. 3: terminals DQ[0:7] for data) and the respective portion of the plurality of metadata bits is read over a third data terminal of the channel (FIG. 3: terminal RDQS for parity bits in read operation, see 7:60-8:3).
Regarding dependent claim 18, Suh teaches correcting the portion of the plurality of data bits associated with one of the plurality of memory devices in the first mode or correcting less than the portion of the plurality of data bits associated with one of the plurality of memory devices in the second mode (FIG. 9: e.g. mode 0010B and mode 0011B perform ECC parity [0:23] and ECC parity [0:15], respectively. It is obvious that mode with ECC parity [0:15] correcting less data bits than mode ECC parity [0023]).
Regarding dependent claim 20, Suh teaches changing between the first mode and the second mode of the memory module (FIG. 3: when host is configured to set mode in register 179, see 22:63-23:6).
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-5, 7-11, 13-18, 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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August 27, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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