DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This Office Action is in response to 01/29/2026 Amendment.
Claims 15, 7-11, 13-18, 20 are pending and examined. Claims 6, 12 and 19 have been cancelled.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-2, 7 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 11,010,304 to Kang et al. (hereafter Kang).
Regarding independent claim 1, Kang teaches a system comprising:
a controller including an error correction circuit (FIG. 1B: main memory controller 116 and ECC 121), wherein the controller is configured to provide a plurality of data bits (FIG. 3: cache line data b0-b31) and the error correction circuit is configured to provide a plurality of module parity bits (FIG. 3: parity bits p0-p4) based on the plurality of data bits and further provide a row address including a row driver select bit (e.g. address bit(s) corresponding to particular word line of a row spanning across 1st to 9th micro-arrays of FIG. 3, see 5:13-18 and 7:25-47) as part of a write operation; and
a memory module (see FIG. 1c) comprising:
a plurality of memory devices each configured to store a portion of the plurality of data bits in a first portion of a memory array selected by the row driver select bit and configured to store a portion of the plurality of module parity bits in a second portion of the memory array non-selected by the row driver select bit (FIG. 4: data bits and parity bits are stored along the same row, see 7:25-47, wherein the 1st to 8th micro arrays 301 are selected for data storage, and 9th micro are not selected for data storage, but parity bits).
Regarding dependent claim 2, Kang teaches wherein the memory module comprises: a plurality of channels, each associated with one of the plurality of memory devices (FIG. 4: e.g. the memory device as shown comprises two channels C1 and C2), each of the plurality of channels comprising a plurality of data terminals, wherein a first set of the plurality of data terminals is configured to receive the portion of the plurality of data bits (FIG. 3: data terminals receiving D0-D7) and an additional one of the plurality of data terminals is configured to receive the portion of the plurality of module parity bits as part of the write operation (FIG. 3: data terminal receiving P).
Regarding dependent claim 7, Kang teaches wherein the memory module is configured to operate in an 8x2p3 mode (FIG. 1b shows eight memory chips 120, FIG. 4 shows each memory chip comprising two ECC storage areas, each area comprises three bits).
Claims 15, 16, 18, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US 9,201,728 to Patapoutian et al. (hereafter Patapoutian).
Regarding dependent claim 15, Patapoutian teaches a method comprising:
selecting a first mode or a second mode for a memory module (FIG. 15: step 222 for memory module 104 of FIG. 1);
selecting a first portion (FIG. 3: selecting 1st to 8th micro-arrays 301) or a second portion (FIG. 3: selecting 9th micro-array 302) of a word line in each of the plurality of memory devices (e.g. particular word line of a row spanning across 1st to 9th micro-arrays of FIG. 3, see 5:13-18 and 7:25-47);
storing a respective portion of a plurality of data bits along the selected one of the first portion [which is selected for data storage] or the second portion [which is non-selected for data storage] of the word line and storing a respective portion of a plurality of module parity bits along the non-selected one of the first portion or the second portion of the word line on each of a plurality of memory devices of the memory module, wherein the plurality of module parity bits is a first number of bits in the first mode and a second number of bits in the second mode (FIG. 15: steps 224-228).
Regarding dependent claim 16, Patapoutian teaches wherein the first number of module parity bits enables correction of a first number of the plurality of data bits and
wherein the second number of module parity bits enables correction of a second number of the plurality of parity bits (e.g. p0 enables correction of data bits b0-b7, see 7:57-67).
Regarding dependent claim 18, Patapoutian teaches correcting the portion of the plurality of data bits associated with one of the plurality of memory devices in the first mode or correcting less than the portion of the plurality of data bits associated with one of the plurality of memory devices in the second mode (this implies when number of bytes in payloads of all code index are different as shown in FIG. 12).
Regarding dependent claim 20, Patapoutian teaches further comprising changing between the first mode and the second mode of the memory module (FIG. 7: via code word analysis engine 140).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-5, 8-11, 13-14, 17 are rejected under 35 U.S.C. 103 as being unpatentable over Kang in view of US 9,201,728 to Patapoutian et al. (hereafter Patapoutian).
Kang teaches, as applied in prior rejection of claim 1, all claimed subject matter except further limitations set forth in the following claim(s).
Regarding dependent claim 3, Patapoutian teaches a memory system comprising a controller and memory module (FIG. 1: controller 102 and memory module 104), wherein the plurality of memory devices each include an inherent mode register configured to put the memory module in a first mode or a second mode (FIG. 7: selected code index, also see FIG. 12 and 3:8-13), wherein in the first mode there are a first number of the plurality of module parity bits and in the second mode there are a second number of the plurality of module parity bits (see FIG. 12).
Since Kang and Patapoutian are both from the same field of endeavor, the purpose disclosed by Patapoutian would have been recognized in the pertinent art of Kang.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to implement the parity scheme of Patapoutian to the memory module of Kang in order to covering any level of BER, including worst case BER (see 2:26-35).
Regarding dependent claim 4, Patapoutian teaches wherein the first number of the plurality of module parity bits enables the error correction circuit to perform a first level of error correction and wherein the second number of the plurality of module parity bits enables the error correction circuit to perform a second level of error correction (see FIGS. 8-9 and 11).
Regarding dependent claim 5, Patapoutian teaches wherein the controller configured to provide a plurality of metadata bits as part of the write operation, and wherein the error correction circuit is configured to generate the plurality of module parity bits based on the plurality of data bits and the plurality of metadata bits (FIG. 4: metadata is updated in local memory 128, see 4:25-26 and 9:53-64).
Regarding independent claim 8, Kang teaches an apparatus comprising:
a plurality of memory devices (FIG. 1b: DIMM 118 comprising a plurality of memory devices) each configured to store a portion of a plurality of data bits (FIG. 3: cache line data b0-b31) along a selected first portion (FIG. 3: storing cache line data b0-b31 in 1st to 8th micro-arrays 301, which are selected for data storage) of a word line (e.g. particular word line of a row spanning across 1st to 9th micro-arrays of FIG. 3, see 5:13-18 and 7:25-47) and to store a portion of a plurality of module parity bits along a non-selected second portion of the word line (FIG. 3: storing parity bits p0-p4 in the 9th micro-array 302, which is not selected for data storage),
a plurality of pseudo-channels , each associated with one of the plurality of memory devices (FIG. 4: e.g. the memory device as shown comprises two channels C1 and C2), each of the plurality of pseudo-channels including a first set of data terminals configured to transmit the associated portion of the plurality of data bits (FIG. 3: data terminals receiving D0-D7) and an additional data terminal configured to transmit the associated portion of the plurality of module parity bits (FIG. 3: data terminal receiving P).
Kang does not teach the strikethrough limitations.
Patapoutian teaches an inherent module settings register configured to set the apparatus in a first mode or a second mode (FIG. 7: for selected code index, also see FIG. 12 and 3:8-13); a plurality of memory devices (FIG. 1: memory module 104 comprising a plurality of memory devices) each configured to store a portion of a plurality of data bits and a portion of a plurality of module parity bits (also see FIG. 12 and 3:8-13), wherein the plurality of module parity bits is a first number of module parity bits in the first mode or a second number of module parity bits in the second mode (see FIG. 12).
Since Kang and Patapoutian are both from the same field of endeavor, the purpose disclosed by Patapoutian would have been recognized in the pertinent art of Kang.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to implement the parity scheme of Patapoutian to the memory module of Kang in order to covering any level of BER, including worst case BER (see 2:26-35).
Regarding dependent claim 9, Patapoutian teaches wherein each of the plurality of memory devices has a first capacity in the first mode or a second capacity in the second mode (FIG. 6 shows different payload, i.e. different data capacity, with different code index).
Regarding dependent claim 10, Patapoutian implicitly suggests wherein each of the plurality of memory devices includes an error correction circuit configured to generate a plurality of parity bits based on the stored portion of the plurality of data bits and the stored portion of the plurality of module parity bits (FIG. 11: when each page of a memory device has different code index, there should be separated ECC for each memory device).
Regarding dependent claim 11, Patapoutian teaches wherein the first number of module parity bits enables a first level of correction of the plurality of data bits and the second number of module parity bits enables a second level of correction of the plurality of data bits (see FIG. 12).
Regarding dependent claim 13, Patapoutian suggests wherein the module settings register is configured to see FIG. 7 and 5:38-55). Patapoutian does not suggest involving a user. However, it would have been obvious to one with ordinary skill in the art to involve user in selection of first/second mode because it’s design choice.
Regarding dependent claim 14, Patapoutian teaches wherein a number of bits of the plurality of data bits is the same in the first mode and the second mode (FIG. 12: when number of bytes in payloads of all code index are the same).
Regarding dependent claim 17, Kang teaches reading the plurality of data bits and the plurality of module parity bits over a plurality of channels, each associated with one of the plurality of memory devices (FIG. 4: e.g. the memory device as shown comprises two channels C1 and C2), wherein respective portion of the plurality of data bits is read over a first and a second data terminal of the channel (FIG. 3: data terminals receiving D0-D7) and the respective portion of the plurality of metadata bits is read over a third data terminal of the channel (FIG. 3: data terminal receiving P).
Response to Arguments
Applicant's arguments filed 01/29/026 have been fully considered but they are not persuasive.
Applicant argues:
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Examiner respectfully disagrees with these statements. As Applicant has admitted in (1), rows of micro-arrays are coupled together by a same word-line. It is obvious that any word line in the macro array 201 is selected in response to a corresponding row address comprising row driver select bit(s). Examiner interprets 1st to 8th micro arrays 301 in FIG. 3 of Kang as the first portion of the memory array, which are selected by the row driver select bit for data storage, and 9th micro array 302 as the second portion of the memory array, which is not selected by the row driver select bit for data storage. With such interpretation, Kang teaches (2) and (3).
Claims 15, 7-11, 13-18, 20 maintain rejected for the reasons set forth above.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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February 19, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824