DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Applicant’s claim for the benefit of provisional application 63/516,823 submitted on 7/31/2023 is acknowledged.
Information Disclosure Statement
The information disclosure statement (IDS) filed on 6/17/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS is considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, 7-9, 11, and 13-17 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yang et al. (US 2018/0061835; hereinafter ‘Yang’).
Regarding claim 1, Yang teaches a microelectronic device (10 and 50, FIGS. 2 and 4, [0019, 0038]), comprising:
a first transistor structure (a first transistor structure including T1b and T1, [0022-0023]); hereinafter ‘Tr1’) comprising multiple vertical levels of channel regions (Tr1 including channel regions of T1b and T1 at different vertical levels, FIGS. 2 and 4, [0027, 0039]; hereinafter ‘Tr1CH’);
a second transistor structure (a second transistor structure including T2b and T2; hereinafter ‘Tr2’) neighboring the first transistor structure (Tr2 neighboring Tr1, FIG. 4) and comprising additional multiple vertical levels of channel regions (Tr2 including channel regions of T2b and T2 at different vertical levels, [0028, 0039]; hereinafter ‘Tr2CH’);
a storage device (38b, [0039]) vertically overlying the first transistor structure and the second transistor structure (38b vertically overlying Tr1 and Tr2, FIG. 4);
a first conductive contact structure (30, FIGS. 2 and 4, [0033]) contacting the first transistor structure (30 contacting Tr1); and
a second conductive contact structure (36, FIGS. 2 and 4, [0033]) contacting the second transistor structure (36 contacting Tr2).
Regarding claim 2, Yang teaches the microelectronic device of claim 1, further comprising a conductive line (BL-1, FIG. 4, [0033]) configured to be in electrical communication with the first transistor structure (BL-1 configured to be in electrical communication with Tr1).
Regarding claim 3, Yang teaches the microelectronic device of claim 2, further comprising an additional conductive line (BL-2, FIG. 4, [0033]) configured to be in electrical communication with the second transistor structure (BL-2 configured to be in electrical communication with Tr2).
Regarding claim 4, Yang teaches the microelectronic device of claim 1, wherein the second transistor structure is horizontally spaced from the first transistor structure in a first horizontal direction (Tr2 laterally displaced from Tr1, FIGS. 2 and 4, [0023, 0049]).
Regarding claim 5, Yang teaches the microelectronic device of claim 4, further comprising:
a conductive line (BL-1, FIG. 4, [0033]) configured to be in electrical communication with the first transistor structure (BL-1 configured to be in electrical communication with Tr1); and
an additional conductive line (BL-2, FIG. 4, [0033]) configured to be in electrical communication with the second transistor structure (BL-2 configured to be in electrical communication with Tr2) and horizontally spaced from the conductive line in a second horizontal direction (BL-2 laterally displaced from BL-1, FIG. 4, [0021-0023]).
Regarding claim 7, Yang teaches the microelectronic device of claim 1, wherein the first conductive contact structure is horizontally offset from the second conductive contact structure (30 horizontally offset from 36, FIG. 4, [0023, 0033]).
Regarding claim 8, Yang teaches the microelectronic device of claim 1, wherein the first conductive contact structure and the second conductive contact structure are configured to be in electrical communication with a same conductive line (30 and 36 configured to be in electrical communication with the same wordline WL, FIGS. 1 and 3, [0016, 0024, 0033]).
Regarding claim 9, Yang teaches the microelectronic device of claim 1, wherein the multiple vertical levels of the channel regions of the first transistor structure are vertically offset from the additional multiple vertical levels of channel regions of the second transistor structure (Tr1CH and Tr2CH vertically offset from one another, FIG. 4).
Regarding claim 11, Yang teaches a memory device (10 and 50, FIGS. 2 and 4, [0019, 0038]), comprising:
an array of memory cells (an array including 12, 12a, 12b, and 12c, [0039]), each memory cell of the array of memory cells (12, 12a, 12b, and 12c) comprising:
a first transistor (T1, T1a, T1b, and T1c, [0039]; hereinafter ‘Tr1’) and a second transistor (T2, T2a, T2b, and T2c; hereinafter ‘Tr2’); and
a capacitor (38, 38a, 38b, and 38c, [0039]; hereinafter ‘CAP’) vertically overlying the first transistor (Tr1) and the second transistor (Tr2) and in electrical communication with each of the first transistor and the second transistor (CAP electrical coupled with Tr1 and Tr2, [0030, 0033]; and
a first conductive line (BL-1, [0033]); and
a second conductive line (BL-2) horizontally spaced from the first conductive line in a first horizontal direction (BL-2 laterally displaced from BL-1, [0021-0023]), at least some of the memory cells of the array of memory cells (12) configured to be in electrical communication with each of the first conductive line and the second conductive line (12 configured to be in electrical communication with BL-1 and BL-2, [0033]).
Regarding claim 13, Yang teaches the microelectronic device of claim 11, wherein:
the first conductive line (BL-1, FIG. 4) is located within horizontal boundaries of the first transistor (BL-1 vertically beneath Tr1); and
the second conductive line (BL-2) is located within horizontal boundaries of the second transistor (BL-2 vertically beneath Tr2).
Regarding claim 14, Yang teaches the microelectronic device of claim 11, wherein the first transistor is vertically spaced from the second transistor (Tr1 laterally displaced from Tr2, FIG. 4, [0023, 0049]).
Regarding claim 15, Yang teaches the microelectronic device of claim 11, further comprising:
a first conductive contact structure (30, FIGS. 2 and 4, [0033]) electrically connecting the first conductive line to the first transistor (30 electrically connecting BL-1 to Tr1); and
a second conductive contact structure (36) electrically connecting the second conductive line to the second transistor (36 electrically connecting BL-2 to Tr2).
Regarding claim 16, Yang teaches the microelectronic device of claim 15, wherein:
the first conductive contact structure (30, FIG. 4) is horizontally spaced from the second conductive contact structure in the first horizontal direction (30 horizontally spaced from 36, [0023, 0033]); and
the first conductive contact structure (30) is horizontally aligned with the second conductive contact structure in a second horizontal direction (30 horizontally aligned with 36).
Regarding claim 17, Yang teaches the microelectronic device of claim 11, wherein the capacitor (CAP, FIGS. 2 and 4) comprises multiple vertical levels of a first electrode material (40, [0031]) a second electrode material (42), and a dielectric material (44, [0032]) between the first electrode material and the second electrode material (44 between 40 and 42; 40, 42, and 44 extending through multiple vertical levels of capacitor 38, FIG.2).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2018/0061835) in view of Sills et al. (US 2019/0139960; hereinafter ‘Sills’).
Regarding claim 6, Yang teaches the microelectronic device of claim 1, but does not teach the microelectronic device wherein the storage device exhibits a substantially rectangular cross-sectional shape.
Sills teaches a microelectronic device (10, FIGS. 9 and 12, [0057]) wherein the storage device exhibits a substantially rectangular cross-sectional shape (capacitors 62 formed in capacitor openings 42, the capacitor openings 42, wherein 42 are rectangular cross-section).
As taught by Sills, one of ordinary skill in the art would utilize and modify the above teaching into Yang to obtain and achieve the microelectronic device wherein the storage device exhibits a substantially rectangular cross-sectional shape as claimed, because a rectangular cross-sectional shape facilities arrangement of the storage devices within the rows-and-columns configuration of a memory-cell array [0003, 0046].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Sills in combination with Yang due to above reason.
Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2018/0061835).
Regarding claim 10, Yang teaches the microelectronic device of claim 1, but does not explicitly teach the microelectronic device wherein the first transistor structure is vertically aligned with the second transistor structure.
Yang, however, teaches a vertically stacked memory cell architectures including multiple memory-cell tiers (FIG. 4, [0038-0041]) and further teaches vertically stacked transistor arrangements (FIG. 8, [0049-0058].
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ and modify the teachings of Yang to obtain and achieve the microelectronic device wherein the first transistor structure is vertically aligned with the second transistor structure as claimed, because vertically aligning the transistor structures increase integration density and reduce device footprint [0014, 0058]. Further, it has been held that that rearranging part of an invention involves only routine skill in the art. In re Japikse, 86 USPQ 70 and it has been held that mere duplication of parts has no patentable significance unless a new and unexpected result is produced, In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2018/0061835) in view of Orlowski et al. (US 2005/0167650; hereinafter ‘Orlowski’).
Regarding claim 12, Yang teaches the microelectronic device of claim 11, where each of the first transistor and the second transistor individually comprises channel regions (Tr1 and Tr2 individually comprises channel regions, FIG. 2 and 4, [0027-0029, 0039])
Yang does not teach that the transistor comprises multiple vertical levels of channel regions.
Orlowski teaches a semiconductor device (10, FIGS. 9-10, [0028-0029]) where a transistor comprises multiple vertical levels of channel regions (a transistor has multiple overlying channel regions 72, 74, and 76).
As taught by Orlowski, one of ordinary skill in the art would utilize and modify the above teaching into Yang to obtain and achieve the memory device where a transistor comprises multiple vertical levels of channel regions as claimed, because vertically stacked channel regions increase effective channel area without increasing layout area, thereby improving transistor performance while maintaining a compact and area-efficient device [0033].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Orlowski in combination with Yang due to above reason.
Claims 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over Yang (US 2018/0061835) in view of Shore et al. (US 2010/0182822; hereinafter ‘Shore’).
Regarding claim 18, Yang teaches an electronic system [0065], comprising:
an input device (a keyboard, touchscreen, or other user input interface of the personal computer, cell phones, etc., [0065]);
an output device (a display, touchscreen, or other output interface of the personal computer, cell phones, etc., [0065]); and
a memory device comprising at least one microelectronic device (200, FIG. 8, [0049]), the at least one microelectronic device (200) comprising:
a vertical stack of transistors (a vertical stack of transistors including T1, 38, and T2, [0053]) comprising vertical pairs of transistors (T1 and T2), the transistors of each of the vertical pairs of transistors vertically spaced from one another (T1 vertically spaced from T2); and
a stack structure (38 and 38a, [0053]) comprising capacitors (38 and 38a are capacitor), each capacitor (38 and 38a) comprising:
a first electrode (40, [0054]) configured to be in electrical communication with a first transistor of a vertical pair of transistors (T1; 40 configured to be in electrical communication with T1, [0030, 0033]); and
a second electrode (42, [0054]) configured to be in electrical communication with a second transistor of a vertical pair of transistors (T2; 42 configured to be in electrical communication with T2, [0030, 0033]).
Yang does not teach that the electronic system comprising: a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device.
Shore teaches an electronic system (600, FIG. 8, [0048]) comprising:
a processor device (676) operably coupled to the input device (672) and the output device (674); and
a memory device (678) operably coupled to the processor device (676).
As taught by Orlowski, one of ordinary skill in the art would utilize and modify the above teaching into Yang to obtain and achieve that the electronic system comprising: a processor device operably coupled to the input device and the output device; and a memory device operably coupled to the processor device as claimed, because it enables the memory array to provide data storage and retrieval functionality for the processor during operation of the electronic system [0017].
Thus, it would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to employ the teaching as taught by Shore in combination with Yang due to above reason.
Regarding claim 19, Yang in view of Shore teaches the microelectronic device of claim 18, each transistor of the vertical pairs of transistors (Yang: T1 and T2, FIG. 8) comprises vertically spaced channel regions (26 of T1 and 32 of T2 vertically spaced, [0027-0028]).
Regarding claim 20, Yang in view of Shore teaches the microelectronic device of claim 18, wherein:
a first transistor of one of the vertical pairs of transistors (Yang: T1, FIG. 8) is in electrical communication with a first conductive line (BL-1, [0059]; T1 is in electrical communication with BL-1); and
a second transistor of the one of the vertical pairs of transistors (T2) is in electrical communication with a second conductive line (BL-2; T2 is in electrical communication with BL-2).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JIYOUNG OH whose telephone number is (703)756-5687. The examiner can normally be reached Monday-Friday, 9AM-5PM EST.
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/JIYOUNG OH/Examiner, Art Unit 2818
/DUY T NGUYEN/Primary Examiner, Art Unit 2818 6/24/26
Prosecution Insights