DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a NON-FINAL OFFICE ACTION in response to the Amendment/ Remarks filed 04/03/2026. Claims 1-20 are pending in the Application, of which Claims 1, 8 and 15 are independent.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 04/15/2026 has been entered.
Response to Arguments
Applicant’s arguments, see Amendment/ Remarks filed 04/03/2026, with respect to the rejection of claims 1-20 under 35 U.S.C. 102(a)(1) as being anticipated by Bennett et al. (Pub. No. US 20220068348), have been fully considered but they are not persuasive, as set forth in the present office action.
Applicant argues that Bennett does not disclose “detect an error in an integrity state of the PRAC counter, the error comprising corruption of one or more bits of the PRAC counter when incrementing the activation count” as amendment in the independent Claims 1, 8 and 15.
In response to Applicant arguments, the Examiner notes the incorporation of the new limitation into the Claims is a new matter which was not described in the specification as originally filed and therefore subject to 112a, first paragraph rejection.
There is nothing in the specification that describes the PRAC counter error is due to the corruption of bits caused during the activation count.
For example, the specification describes in para. [0059] At block 402, a counter error is detected in a PRAC counter of a DRAM. The counter error in the PRAC counter may be detected through several mechanisms. For example, using redundancy and parity checks, regular consistency checks, self-testing mechanisms, error monitoring and logging techniques, and redundancy in counters.
For example, in para. [0048], the PRAC counter 180 can identify patterns indicative of potential issues, such as row hammer attacks, which may lead to data corruption in adjacent or neighboring rows, as discussed below with reference to Fig. 3. However, these potential issues are related to data corruption in adjacent or neighboring rows of the DRAM, and not to the error in the PRAC counter itself.
There is no mention in the specification of the “error comprising corruption of one or more bits of the PRAC counter when incrementing the activation count”.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
The incorporation of the new limitation “detect an error in an integrity state of the PRAC counter, the error comprising corruption of one or more bits of the PRAC counter when incrementing the activation count” into the independent Claims 1, 8 and 15, is a new matter which was not described in the specification as originally filed. There is nothing in the specification that describes the PRAC counter error is due to the corruption of bits caused during the activation count.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bennett et al. (Pub. No. US 20220068348) Pub. Date: 2022-03-03.
Regarding independent Claims 1, 8 and 15, Bennett discloses , comprising:
a system-on-chip (SoC); and a dynamic random-access memory (DRAM) in communication with the SoC, [0026] FIG. 1, computing environment 100 includes microprocessor 101 and memory device 111 connected via channel 110, examples of which include a data bus, a memory bus, or any other suitable interface.
including at least a per row activation counting (PRAC) counter, configured to maintain an activation count for each row of a memory array of the DRAM, [0029] Counter unit 115, in response to the activation of the row caused by the read operation, increments the row activation value represented by the bits in cells 134. Counter unit 115 achieves this step prior to the completion of the read operation and writes-back the row activation count in an incremented state to the subset of the cells in the row that held the row activation count prior to the activation.
detect an error in an integrity state of the PRAC counter, the error comprising corruption of one or more bits of the PRAC counter when incrementing the activation count; [0030] In some implementations, counter unit 115 performs an evaluation of the incremented activation count against service criteria. In such cases, counter unit 115 sets a flag (F) “detect an error” or other such signal to trigger service unit 117 to perform the service. In other cases, counter unit 115 provides the incremented value to service unit 117 to allow service unit 117 to evaluate the incremented count against the service criteria.
transmit a signal to an alert signal logic block in the DRAM once the error in the PRAC counter has been detected; [0031] Service unit 117 is coupled to counter unit 115 and determines whether to perform a service on one or more other rows, offset from the activated row, depending upon whether the row activation count associated with the row satisfied the service criteria, as determined by either itself or counter unit 115. Service unit 117 may refresh, relocate, or zero-out the values in one or more rows adjacent to or nearby row 123 if the incremented activation count has met or exceeded a threshold.
and provide the signal to the SoC. [0031] When this is the case, service unit 117 sends a command to memory array 113 and/or associated circuitry to implement the refresh, relocation, or other such service.
Regarding Claims 2-4, 9-11, 16-8, Bennett discloses an address associated with an activated row of a memory array of the DRAM; [0027] FIG. 1, Memory device 111 includes memory array 113, read buffer 114, counter unit 115, and service unit 117. Memory array 113 includes cells arranged in rows represented by rows 121, 123, and 124. A subset of the cells in each of the rows holds a row activation count for each row, while the remainder of the cells hold data to be read out and sent to microprocessor 101.
Regarding Claims 5-7, 12-14, 19-20, Bennett discloses increment and evaluate the activation counts maintained by the PRAC counter, further monitoring or updating of the PRAC counter based on host-configured behavior, wherein sending the signal to the SoC in response to detecting the error.
[0032] In some implementations, counter unit 115 includes incrementing circuitry that increments the row activation count, as well as alert circuitry that alerts service unit 117 that the row activation count for the row has satisfied the refresh criteria. The incrementing circuitry includes read circuitry that reads out the row activation count from row buffer 114, as well as adder circuitry that increments the row activation count by one or more. The incrementing circuitry also includes write-back circuitry that writes back the row activation count in an incremented state to the row from which it was read.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
US 20250045388 Eckel; Nathan A. et al. [0101] In some examples, the command generation component 640 may be configured as or otherwise support a means for generating, by the first interface, the third signaling including the second command, the second command indicating to refresh a first set of rows of the memory array and a second set of rows that are adjacent to the row based on the alert message indicating that a quantity of activations of the row satisfies a second threshold greater than a first threshold or indicating an error associated with a counter for counting activations of the row.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: June 3, 2026
Non-Final Rejection 20260603
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
Prosecution Insights