DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This is a FINAL OFFICE ACTION in response to the Amendment/ Remarks filed 01/23/2026. Claims 1-20 are pending in the Application, of which Claims 1, 8 and 15 are independent.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 10/29/2025 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the IDS has been considered by the examiner.
Response to Arguments
Applicant’s arguments, see Amendment/ Remarks filed 01/23/2026, with respect to the rejection of claims 1-20 under 35 U.S.C. 102(a)(1) as being anticipated by NAGATA et al. (Pub. No. US 20210241808), have been fully considered and are persuasive. Therefore, the rejection has been withdrawn.
However, upon further consideration, a new ground(s) of rejection is made in view of Bennett et al. (Pub. No. US 20220068348) Pub. Date: 2022-03-03, as set forth in the present office action.
Applicant argues that Nagata does not disclose the limitations, as amended in claim 1, a PRAC counter "configured to maintain an activation count for each row of a memory array of the DRAM," and detecting "an error in an integrity state of the PRAC counter based on an activity of the activation count for a row."
In response to Applicant’s arguments, Bennett discloses the above limitations described in the office action, below.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 1, 8 and 15, “detect an error in an integrity state of the PRAC counter based on an activity of the activation count for a row” is indefinite. It is unclear whether the error is due to the PRAC counter or to the excessive activation count of rows that cause the counter to declare an error. There is nothing in the specification that describes an integrity state of the PRAC counter. According to the specification, if the number of activations for a particular row exceeds a predefined threshold, it may indicate a potential error condition or degradation in memory reliability. It is therefore noted that the limitation “detecting an error” is interpreted as an error due to high activation count for a row and not to the failure of the PRAC counter.
Any claims not specifically mentioned above are rejected because of their dependency on a rejected claim.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Bennett et al. (Pub. No. US 20220068348) Pub. Date: 2022-03-03.
Regarding independent Claims 1, 8 and 15, Bennett discloses , comprising:
a system-on-chip (SoC); and a dynamic random-access memory (DRAM) in communication with the SoC, [0026] FIG. 1, computing environment 100 includes microprocessor 101 and memory device 111 connected via channel 110, examples of which include a data bus, a memory bus, or any other suitable interface.
including at least a per row activation counting (PRAC) counter, configured to maintain an activation count for each row of a memory array of the DRAM, [0029] Counter unit 115, in response to the activation of the row caused by the read operation, increments the row activation value represented by the bits in cells 134. Counter unit 115 achieves this step prior to the completion of the read operation and writes-back the row activation count in an incremented state to the subset of the cells in the row that held the row activation count prior to the activation.
configured to detect an error in an integrity state of the PRAC counter based on an activity of the activation count for a row; [0030] In some implementations, counter unit 115 performs an evaluation of the incremented activation count against service criteria. In such cases, counter unit 115 sets a flag (F) “detect an error” or other such signal to trigger service unit 117 to perform the service. In other cases, counter unit 115 provides the incremented value to service unit 117 to allow service unit 117 to evaluate the incremented count against the service criteria.
transmit a signal to an alert signal logic block in the DRAM once the error in the PRAC counter has been detected; [0031] Service unit 117 is coupled to counter unit 115 and determines whether to perform a service on one or more other rows, offset from the activated row, depending upon whether the row activation count associated with the row satisfied the service criteria, as determined by either itself or counter unit 115. Service unit 117 may refresh, relocate, or zero-out the values in one or more rows adjacent to or nearby row 123 if the incremented activation count has met or exceeded a threshold.
and provide the signal to the SoC. [0031] When this is the case, service unit 117 sends a command to memory array 113 and/or associated circuitry to implement the refresh, relocation, or other such service.
Regarding Claims 2-4, 9-11, 16-8, Bennett discloses an address associated with an activated row of a memory array of the DRAM; [0027] FIG. 1, Memory device 111 includes memory array 113, read buffer 114, counter unit 115, and service unit 117. Memory array 113 includes cells arranged in rows represented by rows 121, 123, and 124. A subset of the cells in each of the rows holds a row activation count for each row, while the remainder of the cells hold data to be read out and sent to microprocessor 101.
Regarding Claims 5-7, 12-14, 19-20, Bennett discloses increment and evaluate the activation counts maintained by the PRAC counter, further monitoring or updating of the PRAC counter based on host-configured behavior, wherein sending the signal to the SoC in response to detecting the error.
[0032] In some implementations, counter unit 115 includes incrementing circuitry that increments the row activation count, as well as alert circuitry that alerts service unit 117 that the row activation count for the row has satisfied the refresh criteria. The incrementing circuitry includes read circuitry that reads out the row activation count from row buffer 114, as well as adder circuitry that increments the row activation count by one or more. The incrementing circuitry also includes write-back circuitry that writes back the row activation count in an incremented state to the row from which it was read.
Prior Art References Cited
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See References Cited on PTO-892 form.
SONG et al. (US 20240370331) see, para. [0030] In another example, if the activated row counter value in the metadata/counter information field 130b of an activated row is higher than a configured threshold, action circuitry 141f may save the current row address and counter value to a register (e.g., in register circuitry 141g) and send an alert to controller 120 (e.g., via alert interface 113 and alert interface 123). In response to the alert, controller 120 may read the register(s) (e.g., using a mode register read command) that are storing the row address and counter value that met/exceeded the threshold.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JAMES C KERVEROS whose telephone number is (571)272-3824. The examiner can normally be reached 9-5.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MARK FEATHERSTONE can be reached at (571) 270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JAMES C KERVEROS/Primary Examiner, Art Unit 2111
Date: February 11, 2026
Final Rejection 20260210
JAMES C. KERVEROS
Primary Examiner, Art Unit 2111
James.Kerveros@USPTO.GOV
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