DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
2. The information disclosure statement (IDS) submitted on 01/08/2026 and 06/17/2024 are considered by the examiner.
Drawings
3. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “testing device 100” and “test head” must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 06/17/2024 and 01/08/2026 are considered by the examiner.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1, 3-5, 13, 15, 16 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 20090096475), hereinafter ‘Yamamoto’, and further in view of Jones et al. (US 11828795), hereinafter ‘Jones’.
Regarding Claims 1, 13 and 15, Yamamoto discloses a semiconductor testing device (Abstract), comprising: a test head (Fig. 3, T test head) comprising: one or more probe heads (Fig. 3, probe heads 7A on probe card 7); and one or more electrical connectors (Para [0004] probe card 7 is electrically connected with test head T; electrical connection interpreted as to electrical connectors), wherein the one or more probe heads, the one or more electrical connectors are connected to one or more devices under test (Fig. 3, wafer W as DUT; Para [0003] probe card 7 held by the card holder 6 and an alignment mechanism 8 for aligning probes 7A of the probe card 7 and electrode pads of the wafer W on the wafer chuck 4. While the wafer chuck 4 is horizontally moved by the XY table 4A, the electrode pads of the wafer W are aligned with the probes 7A), a heating/cooling unit configured to spread and remove heat within at least one device of the one or more devices under test (Para [0003] the wafer W is heated to a predetermined temperature by a temperature controlling mechanism built in the wafer chuck 4; Para [0027] the first temperature control unit 46 controls the temperature controlling mechanism 40 so that the wafer W can be cooled to a temperature required for the low-temperature test. The temperature controlling mechanism 40 includes a heating unit and a cooling unit of Claim 13; Further Fig. 1, temperature control units 46 and 47 work together per Para [0028-0029]); a handler wafer below the one or more devices under test (Fig. 3, wafer chuck 4 below wafer W; Para [0003] wafer chuck 4 which a wafer W is mounted on and is horizontally moved by an XY table 4A); and a fixture configured to support the handler wafer (Fig. 1, body 41 of wafer chuck 4 and Para [0022] base plate 44 for supporting the wafer chuck main body 41), Yamamoto fails to disclose wherein the semiconductor testing device is configured to power up at least one device of the one or more devices under test during testing.
Jones discloses thermal heads and corresponding test systems for independently controlling a one or more components while testing one or more devices under test having a tester electrically coupled with a power connection, further coupled to a device under test and the tester monitors power supplied to the DUT (Col. 12, Lines 52-59) for the benefit of keeping the temperature of the components constant and at the same set point temperature (or within a given range) while the device is being tested as the components may dissipate different amounts of power while under testing conditions due to different functions of and/or tests being performed (Col. 2, Lines 19-26).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date to combine and provide the semiconductor testing device configured to power up at least one device of the one or more devices under test during testing for the benefit of keeping the temperature of the components constant and at the same set point temperature (or within a given range) while the device is being tested since it is known the components may dissipate different amounts of power while under testing conditions due to different functions of and/or tests being performed as taught by Jones in Col. 12, Lines 52-59; Col. 2, Lines 19-26.
Regarding Claim 3, Yamamoto further discloses wherein the one or more devices under test includes at least one of: die under test (DUT), chiplet under test (CUT), wafer under test (WUT) (Para [0001] wafer as tested target object), stacked DUT, stacked CUT, module under test (MUT), or sub-assembly under test (SAUT).
Regarding Claim 4, Yamamoto further discloses wherein the one or more probe heads include the heating/cooling unit (Para [0028-0029] the heaters 43 heat the probes 7A.sub.1 protruding from the wafer chuck main body 41 so that they can be at substantially the same temperature as that of the probes 7A electrically in contact with the wafer W. Since the first and second temperature control units 46 and 47 cooperate with each other, the set temperature of the heaters 43 can be adjusted based on the set temperature of the mounting surface of the wafer chuck main body 41).
Regarding Claim 5, Yamamoto further discloses wherein the fixture is a thermally enabled fixture (Fig. 1, wafer chuck 4 having built-in temperature controlling mechanism 40 which can manage temperature of wafer handler) or a base mechanical stiffener and load support for the handler wafer (Para [0022] base plate 44 for supporting the wafer chuck main body 41).
Regarding Claim 16, Yamamoto further discloses forming the heating/cooling unit within the one or more probe heads (Para [0028-0029] the heaters 43 heat the probes 7A.sub.1 protruding from the wafer chuck main body 41 so that they can be at substantially the same temperature as that of the probes 7A electrically in contact with the wafer W. Since the first and second temperature control units 46 and 47 cooperate with each other, the set temperature of the heaters 43 can be adjusted based on the set temperature of the mounting surface of the wafer chuck main body 41); and forming a thermally enabled fixture or a base mechanical stiffener and load support for the handler wafer (Fig. 1, wafer chuck 4 having built-in temperature controlling mechanism 40 which can manage temperature of wafer handler) or a base mechanical stiffener and load support for the handler wafer (Para [0022] base plate 44 for supporting the wafer chuck main body 41).
Claim(s) 2, 6, 8, 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 20090096475), hereinafter ‘Yamamoto’, in view of Jones et al. (US 11828795), hereinafter ‘Jones’, as applied to claim 1 above and further in view of Lim et al. (US 11782085), hereinafter ‘Lim’.
Regarding Claims 2 and 6, Yamamoto and Jones fail to disclose wherein the one or more probe heads have a pitch ranging from 0.5 micrometer to 150 micrometers and wherein the one or more probe heads are made of Si, Cu, Solder, Al, SiGe, GaN, GaAs, Ni, Pt, Au, Pd, W, Mo, Diamond, AlN, BeO, SiN, and SiO2.
Lim discloses a semiconductor test device and system wherein the system may include microbumps with a pitch and a diameter ranging from a few micrometers to tens of micrometers (Col. 1, Lines 27-30) and microbumps may include nickel (Ni), copper (Cu), tin (Sn), lead (Pb), or the like (Col. 3, Lines 40-51) for the benefit of securing signal bandwidth between heterogeneous semiconductor chips and significantly reducing a delay time caused by wiring circuits.
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date to combine and provide wherein the one or more probe heads have a pitch ranging from 0.5 micrometer to 150 micrometers and wherein the one or more probe heads are made of Si, Cu, Solder, Al, SiGe, GaN, GaAs, Ni, Pt, Au, Pd, W, Mo, Diamond, AlN, BeO, SiN, and SiO2 for the benefit of securing signal bandwidth between heterogeneous semiconductor chips and significantly reducing a delay time caused by wiring circuits as taught by Lim in Col. 3, Lines 40-51.
Regarding Claims 8 and 17, Yamamoto in view of Jones disclose the device according to Claims 1 and 15 above. Yamamoto further discloses a plurality of probes and a plurality of pads, thus having first and second units (Abstract; Para [0003-0005] a probe card provided with a plurality of probes; electrode pads of the wafer W).
Yamamoto and Jones fail to explicitly disclose wherein the first unit comprises at least one of: one or more solder bumps, or one or more microbumps, wherein the first unit has a pitch in a range from about 1 micrometer to about 50 micrometers; and wherein the second unit comprises at least one of: one or more pads, or one or more vias, wherein the second unit has a pitch in a range from about 0.5 micrometer to about 20 micrometers.
Lim teaches a plurality of mircobumps having a pitch in a range from about 1 micrometer to about 50 micrometers and a plurality of pads having a pitch in a range from about 0.5 micrometer to about 20 micrometers (Col. 1, Lines 27-30) for the benefit of securing signal bandwidth between heterogeneous semiconductor chips and significantly reducing a delay time caused by wiring circuits.
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date to combine and provide wherein the first unit comprises at least one of: one or more solder bumps, or one or more microbumps, wherein the first unit has a pitch in a range from about 1 micrometer to about 50 micrometers; and wherein the second unit comprises at least one of: one or more pads, or one or more vias, wherein the second unit has a pitch in a range from about 0.5 micrometer to about 20 micrometers for the benefit of securing signal bandwidth between heterogeneous semiconductor chips and significantly reducing a delay time caused by wiring circuits as taught by Lim in Col. 1, Lines 27-30.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 20090096475), hereinafter ‘Yamamoto’, in view of Jones et al. (US 11828795), hereinafter ‘Jones’, as applied to claim 1 above and further in view of Hirabayashi (US 20210104428), hereinafter ‘Hirabayashi’.
Regarding Claim 7, Yamamoto and Jones fail to explicitly disclose wherein the fixture is made of Si, Glass, Cu, SiGe, GaN, GaAs, W, Mo, Diamond, AlN, BeO, SiN, SiO2.
Hirabayashi discloses it is known that a wafer chuck of ceramic materials are used, such as silicon nitride, to support a substrate in a lithography process step of producing a semiconductor device (Para [0002]).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date to combine and provide wherein the fixture is made of Si, Glass, Cu, SiGe, GaN, GaAs, W, Mo, Diamond, AlN, BeO, SiN, SiO2 for the benefit of providing a known material to support a substrate in a lithography process step of producing a semiconductor device as taught by Hirabayashi in Para [0002].
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 20090096475), hereinafter ‘Yamamoto’, in view of Jones et al. (US 11828795), hereinafter ‘Jones’, in view of Lim et al. (US 11782085), hereinafter ‘Lim’ as applied to claim 8 above and further in view of Kim et al. (US 20060109017), hereinafter ‘Kim’.
Regarding Claim 9, Yamamoto, Jones, and Lim fail to explicitly disclose wherein the semiconductor testing device is configured to exert a force of about 0.1 gram force (gf) per the second unit to about 5 gf per the second unit.
Kim disclose test is carried out by connecting the probe card to a probe testing device and applying a signal to the chip to be tested with probe tips of the probe card being in contact with pads of the chip to be tested using a force of 1 gram force applied between the probe tips of the probe testing device and testing wafer including the chip to be tested for the benefit of determining defectiveness of each of chips after manufacturing the chips on a wafer (Para [0005-0006].
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date to combine and provide wherein the semiconductor testing device is configured to exert a force of about 0.1 gram force (gf) per the second unit to about 5 gf per the second unit for the benefit of providing reliability to endure about one million contacts with the wafer when determining defectiveness of each of chips after manufacturing the chips on a wafer as taught by Kim in Para [0005-0006].
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 20090096475), hereinafter ‘Yamamoto’, in view of Jones et al. (US 11828795), hereinafter ‘Jones’, as applied to claim 1 above and further in view of Medikonda et al. (US 20250219022), hereinafter ‘Medikonda’.
Regarding Claim 10, Yamamoto and Jones fail to disclose one or more interposer layers; one or more accelerator layers; and one or more memory layers.
Medikonda discloses a semiconductor device comprises a wafer with an active interposer (Abstract); one or more accelerator layers (Fig. 5A, 550; Para [0071-0073]); and one or more memory layers (Fig. 5A, 570) for the benefit of providing electrical interface routing between one socket or connection to another of alternative applications of semiconductor chips, resulting in spreading a connection to a wider pitch or to reroute a connection to a different connection (Para [0002]).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date to combine and provide one or more interposer layers; one or more accelerator layers; and one or more memory layers as alternative applications of semiconductor chips and their respective mounting for the benefit of providing electrical interface routing between one socket or connection to another, resulting in spreading a connection to a wider pitch or to reroute a connection to a different connection as taught by Medikonda in Para [0002].
Claim(s) 11 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 20090096475), hereinafter ‘Yamamoto’, in view of Jones et al. (US 11828795), hereinafter ‘Jones’, as applied to claims 1 and 15 above and further in view of Eldridge (WO 0113130 A1), hereinafter ‘Eldridge’.
Regarding Claims 11 and 19, Yamamoto in view of Jones disclose the device according to Claims 1 and 15 above. Yamamoto further discloses one or more thermal sensors (Para [0026] temperature sensor) and one or more test contacts integrated with at least one of: the one or more devices under test (Para [0024-0026] probes 7A.sub.1 protruding from the wafer chuck main body 41 are heated by the heaters 43 during the high-temperature test to substantially the same temperature as that of the probes 7A electrically connected with the wafer W; temperature control unit 46 controls the temperature controlling mechanism 40 so that the wafer W on the mounting surface of the wafer chuck main body 41 can be set at a temperature required for the test).
Yamamoto in view of Jones fail to explicitly disclose at least one of: one or more load sensors, or one or more stress sensors.
Eldridge discloses a device under test comprises a semiconductor wafer containing a plurality of integrated circuits where a stress test is to be performed on the integrated circuit in conjunction with the electrical testing for the benefit of monitoring and achieving a desired temperature for the testing procedures of the integrated circuit (Page 12, Line 30-Page 11, Line 4).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date to combine and provide one or more load sensors, or one or more stress sensors for the benefit of monitoring and achieving a desired temperature for the testing procedures of the integrated circuit as taught by Eldridge in Page 12, Line 30-Page 11, Line 4.
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 20090096475), hereinafter ‘Yamamoto’, in view of Jones et al. (US 11828795), hereinafter ‘Jones’, as applied to claim 1 above and further in view of Wang et al. (US 20250014978), hereinafter ‘Wang’.
Regarding Claim 12, Yamamoto in view of Jones disclose the device according to Claim 1 above. Yamamoto further discloses wherein the semiconductor testing device is configured to test the one or more devices under test within a temperature range from −55° C. to 150° C (Para [0005]).
Yamamoto in view of Jones fail to disclose wherein the semiconductor testing device is configured to test a 3D stacked plurality of devices and a 2D stacked plurality of devices.
Wang teaches a probing test that involves making electrical contact with specific nodes on a semiconductor device using a probe needle wherein the semiconductor testing device is configured to test a 3D stacked plurality of devices (Para [0054] monolithic 3D stacking die; Para [0042] disclosing plurality of devices) and a 2D stacked plurality of devices (Fig. 1A, 142 and 141 on interposer) for the benefit of verifying that a plurality of semiconductor devices, alternatively a 3D stacked device and a 2D stacked plurality of devices, meets the desired performance specifications before it is packaged and shipped to customers.
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date to combine and provide testing for a 3D stacked plurality of devices and a 2D stacked plurality of devices for the benefit of verifying that a plurality of semiconductor devices meets the desired performance specifications before it is packaged and shipped to customers as taught by Wang in Fig. 1A and Para [0042,0054].
Claim(s) 14 and 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 20090096475), hereinafter ‘Yamamoto’, in view of Jones et al. (US 11828795), hereinafter ‘Jones’, as applied to claims 1 and 15 above and further in view of Lai et al. (US 11675340), hereinafter ‘Lai’.
Regarding Claims 14 and 18, Yamamoto and Jones fail to disclose an artificial intelligence unit configured to utilize test data associated with the one or more devices under test to determine at least one of: a first number of probe heads or a second number of electrical connectors to be used for testing a device.
Lai discloses an artificial intelligence unit configured to utilize test data associated with devices under test, such as wafers, to determine and control which tools are used for testing and contacting the wafer (Col. 6, Lines 30-Col. 7 Line 20, 27-56; transfer robot controls tools in contact with wafer while using data analyzed by artificial intelligence to further control which tools are used) for the benefit of notifying a user of damage and controlling a semiconductor manufacturing apparatus (Abstract).
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date to combine and provide an artificial intelligence unit configured to utilize test data associated with the one or more devices under test to determine and control which tools are used for testing and contacting the wafer to be used for testing a device for the benefit of notifying a user of damage and controlling a semiconductor manufacturing apparatus as taught by Lai Col. 6, Lines 30-Col. 7 Line 20, 27-56 and in the Abstract.
Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yamamoto et al. (US 20090096475), hereinafter ‘Yamamoto’, in view of Medikonda et al. (US 20250219022), hereinafter ‘Medikonda’.
Regarding Claim 20, Yamamoto discloses a semiconductor testing device (Abstract), comprising: a test head (Fig. 3, T test head) a handler wafer (Fig. 3, wafer chuck 4; Para [0003] wafer chuck 4 which a wafer W is mounted on and is horizontally moved by an XY table 4A); a fixture configured to support the handler wafer (Fig. 1, body 41 of wafer chuck 4 and Para [0022] base plate 44 for supporting the wafer chuck main body 41) Yamamoto fails to disclose one or more stacked chiplet layers; and one or more interposer layers.
Medikonda discloses one or more stacked chiplet layers; and one or more interposer layers (Para [0002] interposer stacks and combination of chiplets bonded on interposer) for the benefit of providing electrical interface routing between one socket or connection to another of alternative applications of semiconductor chips, resulting in spreading a connection to a wider pitch or to reroute a connection to a different connection (Para [0002]) .
Therefore it would have been obvious to one having ordinary skill in the art before the effective filing date to combine and provide one or more stacked chiplet layers; and one or more interposer layers for the benefit of providing electrical interface routing between one socket or connection to another of alternative applications of semiconductor chips, resulting in spreading a connection to a wider pitch or to reroute a connection to a different connection as taught by Medikonda in Para [0002].
Conclusion
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/ALESA ALLGOOD/ Primary Examiner, Art Unit 2858