Prosecution Insights
Last updated: August 18, 2026
Application No. 18/745,999

TESTING DEVICE FOR TESTING SEMICONDUCTORS

Final Rejection §103
Filed
Jun 17, 2024
Examiner
ALLGOOD, ALESA M
Art Unit
2858
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
International Business Machines Corporation
OA Round
2 (Final)
82%
Grant Probability
Favorable
3-4
OA Rounds
5m
Est. Remaining
99%
With Interview

Examiner Intelligence

Grants 82% — above average
82%
Career Allowance Rate
540 granted / 656 resolved
+14.3% vs TC avg
Strong +18% interview lift
Without
With
+18.4%
Interview Lift
resolved cases with interview
Typical timeline
2y 7m
Avg Prosecution
22 currently pending
Career history
667
Total Applications
across all art units

Statute-Specific Performance

§101
4.3%
-35.7% vs TC avg
§103
49.1%
+9.1% vs TC avg
§102
22.0%
-18.0% vs TC avg
§112
18.3%
-21.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 656 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Response to Arguments Applicant’s arguments, see Remarks, filed 06/10/2026, with respect to the amended Claims 1 and 15 have been fully considered and are persuasive. The 35 U.S.C. 103 of Claims 1-3, 5-19 has been withdrawn. Applicant’s arguments with respect to claim(s) 20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. See new ground of rejection below, necessitated by amendment. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Liu et al. (US 20170227348), and further in view of Bachelder et al. (US 20010050567), hereinafter ‘Bachelder’. Regarding Claim 20, Liu discloses a semiconductor testing device (Fig. 15, 300; Para [0070-0073]), comprising: a test head (Fig. 15, 304 and 305); a handler wafer (Fig. 15, 302) for supporting one or more devices under test (Fig. 15, 301); wherein, during testing, one or more probe heads (Fig. 15, 305 and 306) are adapted to contact the one or more devices under test (Fig. 15, 305, 306 and 307 used to make measurements of wafer 301; Para [0064]) and provide heating or cooling, through contacting, to the one or more devices under test (Para [0064] the probe head includes a localized heat source 307 that heats a region of the wafer 301). Liu fails to explicitly disclose having one or more interposers and one or more probe heads connected to the one or more interposers and a fixture configured to support the handler wafer. Bachelder discloses a testing device having one or more interposers and one or more probe heads connected to the one or more interposers (Claim 7, test head comprising an interposer) and a fixture configured to support the handler wafer (Fig. 8a and 8b, fixture 96 supporting chuck 86; Para [0065-0066] wafer 26 can be clamped to chuck 86) for the benefit of providing space transform wiring and provide connection there between the probe head and board and provide support when realigning the wafer for testing (Para [0016, 0065-0066] Claim 7). Therefore it would have been obvious to one having ordinary skill in the art to combine and provide one or more interposers and one or more probe heads connected to the one or more interposers and a fixture configured to support the handler wafer for the benefit of providing space transform wiring and provide connection there between the probe head and board and provide support when realigning the wafer for testing as taught by Bachelder in Para [0016, 0065-0066] Claim 7. Allowable Subject Matter Claims 1-3, 5-19 are allowed. The following is an examiner’s statement of reasons for allowance: Regarding Claim 1, the closest prior art fails to disclose nor would it be obvious to combine “a semiconductor testing device, comprising: a test head comprising: one or more probe heads; and one or more electrical connectors, wherein the one or more probe heads, the one or more electrical connectors are connected to one or more devices under test, a heating/cooling unit configured to spread and remove heat within at least one device of the one or more devices under test, wherein the one or more probe heads include the heating/cooling unit; a handler wafer below the one or more devices under test; and a fixture configured to support the handler wafer, wherein the semiconductor testing device is configured to power up at least one device of the one or more devices under test during testing” renders the claim allowable over the prior art. All subsequent claims are also allowable due to dependency. All subsequent claims are allowable due to dependency. Regarding Claim 15, the claim is also allowable similarly to Claim 1 for comprising similar allowable subject matter. All subsequent claims are allowable due to dependency. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Conclusion Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a). A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action. Any inquiry concerning this communication or earlier communications from the examiner should be directed to ALESA ALLGOOD whose telephone number is (571)270-5811. The examiner can normally be reached M-F 7:30 AM-3:30 PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eman Alkafawi can be reached at (571) 272-4448. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /ALESA ALLGOOD/Primary Examiner, Art Unit 2858
Read full office action

Prosecution Timeline

Jun 17, 2024
Application Filed
Mar 30, 2026
Non-Final Rejection mailed — §103
May 29, 2026
Interview Requested
Jun 08, 2026
Applicant Interview (Telephonic)
Jun 08, 2026
Examiner Interview Summary
Jun 10, 2026
Response Filed
Jul 07, 2026
Final Rejection mailed — §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

3-4
Expected OA Rounds
82%
Grant Probability
99%
With Interview (+18.4%)
2y 7m (~5m remaining)
Median Time to Grant
Moderate
PTA Risk
Based on 656 resolved cases by this examiner. Grant probability derived from career allowance rate.

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