DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-4, 7, 10-12, and 14-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by KO et al. 9US 20230352509 A1, hereinafter Ko)
With regards to claim 1, Ko discloses an image sensor, (FIGS. 1-5A) comprising:
a semiconductor substrate (substrate 100) having a first conductivity type (first conductivity type, see Paragraph [0048]) and including a first surface (first surface 100a) and a second surface (second surface 100b) opposite to each other;
a plurality of photoelectric conversion regions (photoelectric conversion regions 110) in the semiconductor substrate and having a second conductivity type; (second conductivity type, see Paragraph [0050]) and
a first pixel isolation structure (central pixel isolation pattern 150 and dopant region 33) between the photoelectric conversion regions adjacent to each other in a first direction,
wherein the first pixel isolation structure includes,
a first conductive pattern (barrier dopant region 33) adjacent to the semiconductor substrate and having a shape extending from the first surface to the second surface, (see FIG. 5A)
an inner dielectric pattern (dielectric 151) on an inner lateral surface of the first conductive pattern,
a buried dielectric pattern (dielectric 155) on the inner dielectric pattern, and
an etch stop layer (dielectric 153) between the inner dielectric pattern and the buried dielectric pattern. (See FIG. 4A)
With regards to claim 2, Ko discloses the image sensor of claim 1, further comprising:
a second pixel isolation structure (leftmost isolation structure 150 and 33) between the photoelectric conversion regions adjacent to each other in a second direction diagonal to the first direction,
wherein the second pixel isolation structure includes another portion of the first conductive pattern, a second conductive pattern on the inner lateral surface of the other portion of first conductive pattern, and another portion of the buried dielectric pattern on the second conductive pattern. (See FIGS. 4 and 5A)
With regards to claim 3, Ko discloses the image sensor of claim 2, wherein the first conductive pattern of the second pixel isolation structure has a thickness decreasing with decreasing distance from the first surface of the semiconductor substrate. (See FIG. 5A)
With regards to claim 4, Ko discloses the image sensor of claim 2, wherein a top surface of the first conductive pattern included in the second pixel isolation structure is coplanar with a top surface of the second conductive pattern. (See FIG. 5A)
With regards to claim 7, Ko discloses the image sensor of claim 2, wherein a width in the first direction of the first pixel isolation structure is less than a width in the second direction of the second pixel isolation structure. (See FIG. 5A)
With regards to claim 10, Ko discloses the image sensor of claim 2, wherein the first direction and the second direction are parallel to the first surface and the second surface of the semiconductor substrate. (See FIG. 5A)
With regards to claim 11, Ko discloses the image sensor of claim 1, wherein the etch stop layer includes at least one selected from carbon, silicon, (Paragraph [0054]: “The second isolation pattern 153 may include a crystalline semiconductor material such as poly-silicon.”) argon, and boron.
With regards to claim 12, Ko discloses the image sensor of claim 1, further comprising:
a device isolation layer (isolation layer 103) in the semiconductor substrate and adjacent to the first surface, wherein the first pixel isolation structure penetrates the device isolation layer, and a bottom surface of the device isolation layer is higher than the etch stop layer. (See FIG. 5A)
With regards to claim 14, Ko discloses an image sensor, (FIGS. 1-5A) comprising:
a semiconductor substrate (substrate 100) having a first conductivity type (first conductivity type, see Paragraph [0048]) and including a first surface (first surface 100a) and a second surface (second surface 100b) opposite to each other;
a plurality of photoelectric conversion regions (photoelectric conversion regions 110) in the semiconductor substrate and having a second conductivity type; (second conductivity type, see Paragraph [0050]) and
a device isolation layer (isolation layer 103) in the semiconductor substrate and adjacent to the first surface;
a first pixel isolation structure (central pixel isolation pattern 150 and dopant region 33) between two neighboring ones of the photoelectric conversion regions and including a first etch stop layer;
a second pixel isolation structure (leftmost isolation structure 150 and 33) between four neighboring ones of the photoelectric conversion regions and including a second etch stop layer, (see FIGS. 4 and 5A)
wherein the first etch stop layer and the second etch stop layer are between a bottom surface of the device isolation layer and the second surface of the semiconductor substrate. (See FIG. 5A)
With regards to claim 15, Ko discloses the image sensor of claim 14, wherein the first etch stop layer and the second etch stop layer independently include at least one selected from carbon, silicon, (Paragraph [0054]: “The second isolation pattern 153 may include a crystalline semiconductor material such as poly-silicon.”) argon, and boron.
With regards to claim 16, Ko discloses the image sensor of claim 14, wherein the first pixel isolation structure includes,
an inner dielectric pattern (dielectric 151) between the first etch stop layer and the second surface and a first portion of a first conductive pattern on opposite sides of the inner dielectric pattern, and
wherein the second pixel isolation structure includes,
a second conductive pattern between the second etch stop layer and the second surface, and
a second portion of the first conductive pattern on opposite sides of the second conductive pattern. (See FIG. 5A)
With regards to claim 17, Ko discloses the image sensor of claim 14, wherein each of the first pixel isolation structure and the second pixel isolation structure has a width that decreases in a direction from the first surface to the second surface. (see FIG. 5A)
With regards to claim 18, Ko discloses an image sensor, (FIGS. 1-7) comprising:
a semiconductor substrate (substrate 100) including a light-receiving area, (area above pixel area PX) a light-shielding area, (area having pixel isolation pattern 150) and a pad area (area containing pixels PX1-PX4) and having a first surface (first surface 100a) and a second surface (second surface 100b) opposite to each other; (See FIGS. 5A to 7)
a pixel isolation structure (central pixel isolation pattern 150 and dopant region 33) in the semiconductor substrate on the light-receiving area and the light-shielding area, the pixel isolation structure defining a plurality of pixel regions and including a first conductive pattern; (dopant region 33)
a transfer gate electrode (transfer gate TG) on the first surface of the semiconductor substrate;
a plurality of photoelectric conversion regions (regions 110) in the semiconductor substrate on the light-receiving area and the light-shielding area;
a pixel circuit layer (at least gate electrode GE) on the first surface of the semiconductor substrate; (See FIG. 5A) and
an optical transmission layer (light transmission layer 30) on the second surface of the semiconductor substrate, wherein the pixel isolation structure includes,
a plurality of first pixel isolation structures (left isolation layers 103) between the pixel regions adjacent to each other in a first direction or a second direction intersecting the first direction, and
a plurality of second pixel isolation structures (right isolation layers 103) between the pixel regions adjacent to each other in a third direction diagonal to the first and second directions,
wherein the first pixel isolation structure further includes an inner dielectric pattern (dielectric 151) on an inner lateral surface of the first conductive pattern, and
the second pixel isolation structure further includes a second conductive pattern (doped region 160) on the inner lateral surface of the first conductive pattern. (see FIG. 5A
With regards to claim 19, Ko discloses the image sensor of claim 18, wherein the first direction, the second direction, and the third direction are parallel to the first surface and the second surface. (See FIG. 5A)
With regards to claim 20, Ko discloses the image sensor of claim 18, wherein the first pixel isolation structure further includes:
a buried dielectric pattern (dielectric 155) on the inner dielectric pattern, and
an etch stop layer (dielectric 153) between the inner dielectric pattern and the buried dielectric pattern, (See FIG. 4A)
wherein the etch stop layer includes at least one selected from carbon, silicon, (Paragraph [0054]: “The second isolation pattern 153 may include a crystalline semiconductor material such as poly-silicon.”) argon, and boron.
Allowable Subject Matter
Claims 5-6, 8-9, and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim et al. (US 20200227449 A1) – photoelectric device
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEVEN M Page whose telephone number is (571)272-3249. The examiner can normally be reached M-F: 10:00AM-6:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Christine S. Kim can be reached at 571-272-8548. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEVEN M PAGE/Primary Patent Examiner, Art Unit 2812
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