Prosecution Insights
Last updated: October 01, 2026
Application No. 18/746,534

PRINTED CIRCUIT BOARD

Non-Final OA §102
Filed
Jun 18, 2024
Priority
Aug 01, 2023 — RE 10-2023-0100479
Examiner
BURNS, TREMESHA WILLIS
Art Unit
2847
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Samsung Electro-Mechanics Co., Ltd.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
2m
Est. Remaining
95%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
698 granted / 893 resolved
+10.2% vs TC avg
Strong +17% interview lift
Without
With
+17.2%
Interview Lift
resolved cases with interview
Typical timeline
2y 6m
Avg Prosecution
43 currently pending
Career history
947
Total Applications
across all art units

Statute-Specific Performance

§101
0.3%
-39.7% vs TC avg
§103
33.4%
-6.6% vs TC avg
§102
47.0%
+7.0% vs TC avg
§112
17.8%
-22.2% vs TC avg
Black line = Tech Center average estimate • Based on career data from 893 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1 – 18 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Baek et al. (U.S. Patent Publication No. 2017/0202083). Regarding claim 1, in Figure 1, Baek discloses a printed circuit board comprising: a first substrate portion (comprising 105, 185) including a first insulating portion (105) and a plurality of first wiring layers (130, 120) respectively disposed on or in the first insulating portion; a resin layer (155, paragraph [0053]) disposed to cover a side surface of the first insulating portion; and a second substrate portion (comprising 180, 187) including a second insulating portion (180, 187) disposed to cover each of an upper surface of the first insulating portion and an upper surface of the resin layer, and a second wiring layer (160, 165) disposed on or in the second insulating portion. Regarding claim 2, Baek discloses wherein the second wiring layer includes a wiring finer than a wiring of the first wiring layer (Figure 1). Regarding claim 3, Baek discloses wherein the second insulating portion covers at least a portion of the first wiring layer (Figure 1). Regarding claim 4, Baek discloses wherein a side surface of the second insulating portion is substantially coplanar with a side surface of the resin layer (Figure 1). Regarding claim 5, Baek discloses wherein at least a portion of the second wiring layer is disposed on an upper region of the resin layer (Figure 1). Regarding claim 6, Baek discloses a third substrate portion including a third insulating portion disposed on a lower side of the first insulating portion, and a third wiring layer disposed on the third insulating portion (Figure 1). Regarding claim 7, Baek discloses wherein the third insulating portion covers a lower surface of the resin layer (Figure 1). Regarding claim 8, Baek discloses wherein the third insulating portion includes a material substantially the same as a material of the second insulating portion (Figure 1). Regarding claim 9, Baek discloses a solder resist layer disposed on each of the second insulating portion and the third insulating portion (Figure 1). Regarding claim 10, Baek discloses wherein a side surface of the solder resist layer is substantially coplanar with a side surface of the second insulating portion and a side surface of the resin layer (Figure 1). Regarding claim 11, Baek discloses a fourth substrate portion including a fourth insulating portion disposed on side surfaces of the second and third insulating portions and a side surface of the resin layer, and a fourth wiring layer disposed on or in the fourth insulating portion (Figure 1). Regarding claim 12, Baek discloses wherein the fourth insulating portion includes a fourth-first insulating portion and a fourth-second insulating portion, the fourth-first insulating portion includes a material substantially the same as a material of the first insulating portion, and the fourth-second insulating portion includes a material substantially the same as a material of the second insulating portion (Figure 1). Regarding claim 13, Baek discloses wherein the fourth wiring layer includes a fourth-first wiring layer and a fourth-second wiring layer, the fourth-first wiring layer includes a wiring having a density substantially the same as that of a wiring of the first wiring layer, and the fourth-second wiring layer includes a wiring having a density substantially the same as that of a wiring of the second wiring layer (Figure 1). Regarding claim 14, Baek discloses wherein the fourth-second insulating portion and the second insulating portion are one integral insulating portion (Figure 1). Regarding claim 15, Baek discloses wherein the fourth substrate portion includes a metal block passing through at least a portion of the fourth insulating portion, the metal block connected to the fourth wiring layer (Figure 1). Regarding claim 16, Baek discloses wherein the resin layer includes at least one of a thermal interface material (TIM), a bonding sheet, an epoxy molding compound (EMC), or an underfill resin (Figure 1). Regarding claim 17, in Figure 1, Baek discloses a printed circuit board comprising: a first substrate portion (comprising 105, 185) including a first insulating portion (105) and a first wiring layer (130, 120) disposed on or in the first insulating portion; a resin layer (155, paragraph [0053]) disposed to cover a side surface of the first substrate portion; and a second substrate portion (comprising 180, 187) including a second insulating portion (180, 187) disposed on the first insulating portion and the resin layer, and a second wiring layer (160, 165) disposed on or in the second insulating portion, wherein an upper surface of the resin layer is substantially coplanar with an upper surface of the first insulating portion (Figure 7). Regarding claim 18, Baek discloses wherein a side surface of the resin layer is externally exposed, and a side surface of the second insulating portion is substantially coplanar with the side surface of the resin layer (Figure 1). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to TREMESHA W BURNS whose telephone number is (571)270-3391. The examiner can normally be reached Monday-Friday 8am - 4:30 pm EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Timothy Thompson can be reached at (571) 272-2342. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. TREMESHA W. BURNS Primary Examiner Art Unit 2847 /TREMESHA W BURNS/Primary Examiner, Art Unit 2847
Read full office action

Prosecution Timeline

Jun 18, 2024
Application Filed
Sep 22, 2026
Non-Final Rejection mailed — §102 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
95%
With Interview (+17.2%)
2y 6m (~2m remaining)
Median Time to Grant
Low
PTA Risk
Based on 893 resolved cases by this examiner. Grant probability derived from career allowance rate.

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