Prosecution Insights
Last updated: October 02, 2026
Application No. 18/746,857

SEMICONDUCTOR APPARATUS

Non-Final OA §102
Filed
Jun 18, 2024
Priority
Nov 14, 2023 — RE 10-2023-0157694
Examiner
PHAM, LONG
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
92%
Grant Probability
Favorable
1-2
OA Rounds
0m
Est. Remaining
97%
With Interview

Examiner Intelligence

Grants 92% — above average
92%
Career Allowance Rate
1530 granted / 1671 resolved
+31.6% vs TC avg
Moderate +6% lift
Without
With
+5.5%
Interview Lift
resolved cases with interview
Typical timeline
2y 4m
Avg Prosecution
40 currently pending
Career history
1697
Total Applications
across all art units

Statute-Specific Performance

§101
0.1%
-39.9% vs TC avg
§103
42.7%
+2.7% vs TC avg
§102
39.7%
-0.3% vs TC avg
§112
10.3%
-29.7% vs TC avg
Black line = Tech Center average estimate • Based on career data from 1671 resolved cases

Office Action

§102
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Election/Restrictions Applicant’s election without traverse of claims 1, 3-15 in the reply filed on 12/26/24 is acknowledged. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Campbell et al. (US pat 9113581). With respect to claim 1, Campbell et al. teach a semiconductor apparatus comprising (see figs. 1-14, particularly figs. 5A, 8, and 11 and associated text): a semiconductor chip 500 comprising a semiconductor integrated circuit 511; a cooling channel 821, 822, 811 at least partially in the semiconductor chip and comprising a fine pattern (parts between 822) on at least a portion of a wall surface of the cooling channel, the fine pattern configured to generate inherently a capillary pressure that induces a flow of a liquid coolant (via 810); and a temperature controller (col. 5, lines 30-45) configured to control a supply temperature of the liquid coolant supplied to the cooling channel. Claim(s) 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Campbell et al. (US pat 9113581). With respect to claim 14, Campbell et al. teach a semiconductor apparatus comprising (see figs. 1-14, particularly figs. 5A, 8, and 11 and associated text): a semiconductor chip 500 comprising a semiconductor integrated circuit 511; a plurality of cooling channels 821, 822, 811 at least partially in the semiconductor chip, each of the plurality of cooling channels comprising a fine pattern (parts between 822) on at least a portion of a wall surface of a respective cooling channel of the plurality of cooling channels, each of the fine patterns being configured to generate inherently a capillary pressure that induces a flow of a liquid coolant; and a temperature controller (col. 5, lines 40-45) configured to control a supply temperature of the liquid coolant supplied to the plurality of cooling channels. With respect to claim 15, Campbell et al. teach a package housing at least partially surrounding the semiconductor chip, the package housing comprising at least one first opening 830, 111, 1122 configured to discharge vapor coolant and a plurality of second openings 810,820, 1110, 1120 respectively corresponding to the plurality of cooling channels and configured to apply the liquid coolant to respective cooling channels of the plurality of cooling channels. See figs. 5A, 8, and 11 and associated text. Allowable Subject Matter Claims 3-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Examiner’s Cited References The cited references generally show the similar or related structure having a package having an IC, a cooling unit having a cooling channel and a fine pattern on wall of channel, and a liquid coolant, and a temperature controller for liquid coolant as presently claimed by applicant. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to LONG PHAM whose telephone number is (571)272-1714. The examiner can normally be reached Mon-Friday. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jacob Choi can be reached at 469-295-9060. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. LONG . PHAM Examiner Art Unit 2823 /LONG PHAM/Primary Examiner, Art Unit 2897
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Prosecution Timeline

Jun 18, 2024
Application Filed
Sep 16, 2026
Non-Final Rejection mailed — §102 (current)

Precedent Cases

Applications granted by this same examiner with similar technology

Patent 12751320
CHIP-ON-WAFER-ON-BOARD STRUCTURE USING SPACER DIE AND METHODS OF FORMING THE SAME
4y 3m to grant Granted Sep 29, 2026
Patent 12745645
Integrated Circuit Packages and Methods of Forming the Same
3y 8m to grant Granted Sep 22, 2026
Patent 12745684
SEMICONDUCTOR PACKAGE AND METHOD OF MANUFACTURING THE SAME
3y 6m to grant Granted Sep 22, 2026
Patent 12740475
SILICON NITRIDE LINER FOR PROMOTION OF MOLD ADHESION IN INTEGRATED CIRCUITS
5y 0m to grant Granted Sep 15, 2026
Patent 12738918
DIE PACKAGE WITH SEALED DIE ENCLOSURES
4y 0m to grant Granted Sep 15, 2026
Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
92%
Grant Probability
97%
With Interview (+5.5%)
2y 4m (~0m remaining)
Median Time to Grant
Low
PTA Risk
Based on 1671 resolved cases by this examiner. Grant probability derived from career allowance rate.

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