Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Species III as drawn to FIG. 11 relating to a follow-up process performed after S7 illustrated in FIG. 6 (Claims 1-22) in the reply filed on 08/05/2026 is acknowledged.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 5-10, 14, 17-19 and 21-22 is/are rejected under 35 U.S.C. 102(a)(1)/(2) as being anticipated by Arisumi (Pub. No.: US 2015/0228663).
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Re claim 1, Arisumi, FIG. 23 [flip it upside down] [as shown above] teaches a semiconductor memory device, comprising:
a gate stacked body (100);
an insulating layer (41) overlapping the gate stacked body;
a first source layer (13) including a horizontal portion between the gate stacked body and the insulating layer and protrusions extending from the horizontal portion, wherein upper surfaces of the protrusions [FSofFSL] protrude toward the insulating layer and lower surfaces of the protrusions protrude toward the insulating layer;
a channel layer (20) penetrating the gate stacked body;
a first memory pattern (left 30, FIG. 16) between the channel layer and the gate stacked body (100); and a second source layer (14) disposed between the gate stacked body and the first source layer.
Re claim 2, Arisumi, FIG. 23 [flip it upside down] [as shown above] teaches the semiconductor memory device according to claim 1, wherein the second source layer (14) surrounds the channel layer (20).
Re claim 5, Arisumi, FIG. 23 [flip it upside down] [as shown above] teaches the semiconductor memory device according to claim 1, wherein the channel layer (20) extends into the horizontal portion of the first source layer (13).
Re claim 6, Arisumi, FIG. 23 [flip it upside down] [as shown above] teaches the semiconductor memory device according to claim 5, further comprising a second memory pattern (right 30) disposed between the first source layer (13) and the channel layer (20).
Re claim 7, Arisumi, FIG. 23 [flip it upside down] [as shown above] teaches the semiconductor memory device according to claim 1, wherein the gate stacked body includes alternately stacked interlayer insulating layers (72) and conductive patterns (70) that surround the channel layer (20).
Re claim 8, Arisumi, FIG. 23 [flip it upside down] [as shown above] teaches the semiconductor memory device according to claim 7, wherein the interlayer insulating layers (72) extend so as to be overlapped by a portion of each of the protrusions of the first source layer (13).
Re claim 9, Arisumi, FIG. 23 [flip it upside down] [as shown above] teaches the semiconductor memory device according to claim 1, wherein: the first source layer includes a first surface [FSofFSL] contacting the insulating layer and a second surface [SSofFSL] opposite the first surface, and the second surface of the first source layer includes a groove defined by the protrusions of the first source layer.
Re claim 10, Arisumi, FIG. 23 [flip it upside down] [as shown above] teaches the semiconductor memory device according to claim 1, further comprising a core insulating layer (50) penetrating the gate stacked body, wherein: the channel layer (20) surrounds a sidewall of the core insulating layer, and the channel layer extends between the core insulating layer and the first source layer (13) so as to close an end portion of the core insulating layer facing the first source layer.
Re claim 14, Arisumi, FIG. 23 [flip it upside down] [as shown above] teaches a semiconductor memory device, comprising:
a first gate stacked body [FGS] surrounding a first channel structure;
a second gate stacked body [SGS] adjacent to the first gate stacked body and surrounding a second channel structure;
a third gate stacked body [TGS] adjacent to the second gate stacked body and surrounding a third channel structure;
vertical insulating structures including a first vertical insulating structure [FC] between the first gate stacked body and the second gate stacked body and a second vertical structure [SC] between the second gate stacked body and the third gate stacked body;
a first source layer including: protrusions including a first protrusion [FP] overlapping the first vertical insulating structure and a second protrusion [SP] overlapping the second vertical insulating structure;
a first horizontal portion [FHP] extending from the first protrusion to overlap the first channel structure and the first gate stacked body;
a second horizontal portion [SHP] extending from the first protrusion and the second protrusion to overlap the second channel structure and the second gate stacked body; and
a third horizontal portion [THP] extending from the second protrusion to overlap the third channel structure [TC] and the third gate stacked body; and
a second source layer (14) surrounding the first channel structure between the first source layer and the first gate stacked body, surrounding the second channel structure between the first source layer and the second gate stacked body, and surrounding the third channel structure between the first source layer and the third gate stacked body,
wherein upper surfaces of the protrusions protrude ([FP]/SP]) in a direction away from the vertical insulating structures, and lower surfaces of the protrusions (middle portion) protrude in the same direction.
Re claim 17, Arisumi, FIG. 23 [flip it upside down] [as shown above] teaches the semiconductor memory device according to claim 14, further comprising:
first memory patterns (30) disposed respectively between the first gate stacked body [FGS] and the first channel structure, between the second gate stacked body [SGS] and the second channel structure [SC], and between the third gate stacked body [TGS] and the third channel structure [TC]; and
second memory patterns (30 of upper portion which are separated by 13) disposed respectively between the first channel structure and the first source layer, between the second channel structure and the first source layer, and between the third channel structure and the first source layer, wherein the second memory patterns are spaced apart from the first memory patterns by the second source layer.
Re claim 18, Arisumi, FIG. 23 [flip it upside down] [as shown above] teaches the semiconductor memory device according to claim 14, wherein each of the protrusions ([FP]/[SP]) has a groove facing the vertical insulating structures, and wherein the groove of the each of the protrusions is defined by a curved shape.
Re claim 19, Arisumi, FIG. 23 [flip it upside down] [as shown above] teaches the semiconductor memory device according to claim 14, wherein the vertical insulating structures (50) extend into the second source layer.
Re claim 21, Arisumi, FIG. 23 [flip it upside down] [as shown above] teaches the semiconductor memory device according to claim 14, wherein:
each of the first gate stacked body [FGS], the second gate stacked body [SGS], and the third stacked body [TGS] includes alternately stacked interlayer insulating layers (72) and conductive patterns (70), and
each of the first channel structure, the second channel structure, and the third channel structure includes:
a core insulating layer (50) penetrating the interlayer insulating layers and the conductive patterns; and
a channel layer (20) surrounding a sidewall of the core insulating layer and extending between the core insulating layer and the first source layer so as to close an end portion of the core insulating layer facing the first source layer.
Re claim 22, Arisumi, FIG. 23 [flip it upside down] [as shown above] teaches a semiconductor memory device, comprising:
a gate stacked body surrounding a channel structure;
a first vertical insulating structure [FC] and a second vertical insulating [SC] structure spaced apart from each other with the gate stacked body interposed therebetween;
a first source layer including:
a horizontal portion [FHP] overlapping the gate stacked body;
a first protrusion [FP] extending from a first side of the horizontal portion to overlap the first vertical insulating structure; and
a second protrusion [SP] extending from a second side of the horizontal portion to overlap the second vertical insulating structure [SC]; and
a second source layer (14) surrounding the channel structure between the first source layer (13) and the gate stacked body, wherein upper surfaces of the first and second protrusions protrude in a direction away from the first and second vertical insulating structures, and lower surfaces of the first and second protrusions protrude in the same direction.
Claim(s) 3-4 and 15-16 is/are rejected under 35 U.S.C. 103 as being unpaArisumi teaches all the limitation of claim 1/14.
Arisumi fails to teach the limitation of claim 3-4 and 15-16.
LEE teaches the first source layer includes a conductive material (101 with tungsten material, [0082]), and the first source layer has a lower resistivity than the second source layer (136 with polysilicon material, [0107]) (claim 3/15);
the first source layer includes at least one of a tungsten layer and a cobalt silicide layer (101, [0082]), and the second source layer includes a doped semiconductor layer (136, [0107]).
In re claim 4, LEE differs from the invention by not showing the first source layer includes at least one of a tungsten silicide layer (claim 4/16).
However, it would have been obvious to one having ordinary skill in the art at the time of the invention was made to include the above said teaching because tungsten silicide making a better contact material since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 277 F.2d 197, 125 USPQ 416.
It would have been obvious to modify Arisumi to include the lower resistive material of LEE to enhance the connectivity, because LEE discloses the source layers (101/136, [0082]/[0107]), and Arisumi recognizes the desirability of adding tungsten silicide layer (12/13/14).
Claim(s) 11-12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arisumi in view of CHOI (Pub. No.: US 2019/0305096).
Arisumi teaches all the limitation of claims 1-2.
Arisumi fails to teach the limitation of claim 11/12.
CHOI teaches further comprising a contact plug (SS) directly contacting at least a portion of the protrusions of the first source layer (SC, FIG. 1A, [0044]) (claim 11);
further comprising a metal source line (BM) electrically coupled to the first source layer (SS) via the contact plug (CS) (claim 12).
It would have been obvious for a person of ordinary skill in the art before the effective filing date of the claim invention to include the above said teaching for the purpose of improving the operational reliability of the semiconductor devices as taught by CHOI, Abstract.
Claim(s) 13 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Arisumi in view of CHOI and further in view of HATTORI (Pub. No.: US 2014/00985).
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HATTORI teaches an upper insulating layer [UIL] covering the insulating layer and the protrusions and being penetrated by the contact plug [CP]; and power lines [PL] spaced apart from the metal source line and overlapping the gate stacked body (ML), wherein the insulating layer and the upper insulating layer are interposed between the power lines and the gate stacked body (claim 13).
a contact plug [CP] contacting at least a portion of the protrusions and extending in a direction opposite a direction facing the vertical insulating structures;
a metal source line [CSL] electrically coupled to the first source layer via the contact plug; and
power lines [PL] spaced apart from the metal source line and overlapping the first gate stacked body and the second gate stacked body (claim 20).
It would have been prima facie obvious to one of ordinary skill in the art at the time the invention was made to include the above said teaching for the purpose of electrically connecting a memory unit MU to the circuit unit CU as taught by HATTORI, [0042].
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONY TRAN whose telephone number is (571)270-1749. The examiner can normally be reached Monday-Friday, 8AM-5PM, EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Britt Hanley can be reached on 571-270-3042. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONY TRAN/Primary Examiner, Art Unit 2894
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