DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant's election with traverse of Group II including claims 15-20 in the reply filed on 12/26/2025 is acknowledged. The traversal is on the ground(s) that independent claim 1 as amended and independent claim 15 are not distinct species. This is found persuasive. Claims 1-14 and 15-20 are rejoined for examination.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 and 15 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by PGPub. 2018/0182449 to Kim et al. (hereafter Kim).
Regarding independent claim 1, Kim teaches a semiconductor memory device, comprising:
a plurality of memory blocks each including at least one memory cell (FIG. 9: cell arrays 910, 110_1, 110_2 … 110_n, 920);
a plurality of first sense amplifier blocks connected between the plurality of memory blocks, and including a first bit line, a first complementary bit line, and a plurality of transistors (FIG. 9: sense amplifiers 150_2 and 150_3); and
a plurality of second sense amplifier blocks electrically connected to outermost memory blocks among the plurality of memory blocks, and including a second bit line, a second complementary bit line, and a plurality of transistors (FIG. 9: sense amplifier 150_1 and 150_n),
wherein: each of the plurality of first sense amplifier blocks and the plurality of second sense amplifier blocks is configured to sense a voltage change of a respectively corresponding bit line, and to adjust a voltage of a sensing bit line and a complementary sensing bit line, based on the sensed voltage change (i.e. offset cancellation, see Background and Summary).
Regarding independent claim 15, Shin teaches a semiconductor memory device, comprising:
a plurality of memory blocks, each memory block among the plurality of memory blocks including at least one memory cell (FIG. 9: cell arrays 910, 110_1, 110_2 … 110_n, 920); and
a plurality of sense amplifier blocks including a first sense amplifier block (FIG. 9: sense amplifiers 150_2 and 150_3) and a second sense amplifier block (FIG. 9: sense amplifier 150_1 and 150_n),
wherein the first sense amplifier block includes a first bit line and a first complementary bit line, and is connected between at least two memory blocks among the plurality of memory blocks (see FIG. 3 as sense amplifiers 150_2 and 150_3),
wherein the second sense amplifier block (sense amplifier 150_1 and 150_n) includes a second bit line (FIG. 3: BL), a second complementary bit line (FIG. 3: BLB), a sensing bit line (FIG. 3: SABL) and a complementary sensing bit line (FIG. 3: SABLB), and is connected to an outermost memory block among the plurality of memory blocks, and
wherein the second sense amplifier block is configured to sense a voltage change in the second bit line, and adjust an output voltage at the sensing bit line and the complementary sensing bit line based on the voltage change of the second bit line (i.e. offset cancellation, see Background and Summary).
Allowable Subject Matter
Claims 2-14, 16-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
With respect to dependent claim 2: wherein the plurality of transistors included in each of the plurality of second sense amplifier blocks include: a first selection transistor and a second selection transistor connected to the complementary sensing bit line in parallel, a first transistor connected to the first selection transistor, and controlled by a voltage change of the complementary sensing bit lines, and a second transistor connected to the second selection transistor, and controlled by a voltage change of the sensing bit line.
With respect to dependent claim 16: wherein the second sense amplifier block further includes: a first selection transistor and a second selection transistor connected to the complementary sensing bit line in parallel, a first transistor connected to the first selection transistor, and controlled by a voltage change of the complementary sensing bit line, and a second transistor connected to the second selection transistor, and controlled by a voltage change of the sensing bit line.
Conclusion
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January 20, 2026
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824
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