FINAL ACTION
DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 06/16/2026 have been fully considered but they are not persuasive.
Contrary to the remarks, although the amendment, which adds the limitation “… and connected in parallel with the output capacitor,” is considered to have overcome the Tang et al. reference, this feature is however found from further search and consideration.
The grounds for the rejection of the amended claims can be found below.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tang et al. (US Pat Pub 9,436,197) in view of Kim et al. (US Pat Pub 2020/0028435) or Ito (US Pat pub 2015/0091664).
Regarding claims 1 and 20, Tang et al. disclose an electronic device (figs. 1 – 5 and all related texts) comprising:
a voltage regulator (mainly referred to as op amp 110 and pass device 120, fig. 1) configured to convert an input voltage (VAA, fig. 1) to generate an output voltage (Vreg, fig. 1) through an output node (at Vreg/Iload node, fig. 1);
a load device (referred to as RL as part of 101, fig. 1) configured to receive the output voltage (Vreg);
an output capacitor connected to the output node (referred to as CL), the output capacitor having a fixed capacitance (referred to as Load capacitance with fixed capacitance of the particular load device);
a capacitance controller (130, fig. 1) configured to generate a plurality of capacitance control signals based on a state signal indicating an operation state of the electronic device (output of 150 to Variable capacitance device 160 based on load current, see col. 2, lines 53 – 58); and
a variable capacitance circuit (160, fig. 1) connected to the output node (as shown at node Vreg in fig. 1), the variable capacitance circuit having a capacitance that changes based on the plurality of capacitance control signals (col. 4, lines 7 – 23).
Tang et al. disclose the electronic device as set forth above, except the variable capacitance circuit connected to the output node is also connected in parallel with the output capacitor. The feature is however taught by:
Kim et al. (US Pat Pub 2020/0028435) disclose variable capacitor 13 of the switching regulator circuit 10 of fig. 1, the variable capacitor 13 connected across the Vout node and ground, and controlled by control signal C_CL. This variable capacitance circuit connection would be in parallel configuration with the output load 101 of Tang et al.
And Ito (US Pat Pub 2015/0091665) also disclose in fig. 4 variable capacitance circuits 60-2/62-2 connected between output node NB2 and ground node, which is also parallel with the output circuit 54, which, when combined with the Tang et al. reference, is that of the output load 101, and also being parallel with the output capacitor CL of load 101.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the application, to combine the references as cited, so that fluctuation is minimized … (see para 0113 in Ito).
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et (US Pat Pub 2022/0197520) in view of Potanin et al. (US Pat Pub 2015/0349631) (OR in view of Tang et al. in US Pat 9,436,197), and further in view of Kim et al. (US Pat Pub 2020/0028435) or Ito (US Pat pub 2015/0091664).
Regarding claim 15, Kobayashi et al. disclose the storage device (for example fig. 1 and all related texts) comprising:
a nonvolatile memory device configured to store data (for example NAND memory 16, fig. 1, para 0027);
a storage controller configured to control the nonvolatile memory device (referred to as the NAND controller 38, see para 0038).
a voltage regulator (for example power supply circuit 22, fig. 2) configured to convert an input voltage (referred to as external power supply, fig. 2) to generate an output voltage (see all the outputs from circuit 22 in fig. 2), and configured to supply the output voltage to the nonvolatile memory device and the storage controller (referred to as the output to controller 18 and the outputs to NAND memory 16, fig. 2).
Kobayashi et al. disclose the storage device as shown above, except:
an output capacitor connected to the output node, the output capacitor having a fixed capacitance;
a capacitance controller configured to generate a plurality of capacitance control signals based on a state signal indicating an operation state of the electronic device; and
a variable capacitance circuit connected to the output node, the variable capacitance circuit having a capacitance that changes based on the plurality of capacitance control signals.
However, these features are taught by Potanin et al. (OR Tang et al. as shown above), (including the above-claimed “voltage regulator” limitation as follows):
a voltage regulator (“voltage regulator implemented as an IC may include a power transistor 104, para 0021, fig. 1) configured to convert an input voltage (Vin) to generate an output voltage (Vout) through an output node (referred to as the output node of power transistor 104 where Load device L and output capacitance CL is connected thereto, fig. 1);
an output capacitor connected to the output node (referred to as CL connected to the output node as shown in fig. 1), the output capacitor having a fixed capacitance (capacitance is fixed due to particular characteristic of load device 118);
a capacitance controller (referred to as error amplifier 106 and unity gain buffer 114, fig. 1, para 0023) configured to generate a plurality of capacitance control signals based on a state signal indicating an operation state of the electronic device (output of amp 106 and buffer 114, depending on the operation of the diagram 100 with respect to the connected load device 118); and
a variable capacitance circuit connected to the output node (referred to as Cc 120 and Cu 122, fig. 1) having a capacitance that changes based on the plurality of capacitance control signals (see para 0021, 0023 and 0030).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to combine the features taught by the prior arts as cited, so that output power is consistent for variable applicable loads to the power supply circuit for optimized performance (see abstract in Potanin et al.).
Kobayashi et (US Pat Pub 2022/0197520) in view of Potanin et al. (US Pat Pub 2015/0349631) (OR in view of Tang et al. in US Pat 9,436,197) disclose the storage device as set forth above, except the variable capacitance circuit connected to the output node is also connected in parallel with the output capacitor. The feature is however taught by:
Kim et al. (US Pat Pub 2020/0028435) disclose variable capacitor 13 of of the switching regulator circuit 10 of fig. 1, the variable capacitor 13 connected across the Vout node and ground, and controlled by control signal C_CL. This variable capacitance circuit connection would be in parallel configuration with the output load 101 of Tang et al.
And Ito (US Pat Pub 2015/0091665) also disclose in fig. 4 variable capacitance circuits 60-2/62-2 connected between output node NB2 and ground node, which is also parallel with the output circuit 54, which, when combined with the Tang et al. reference, is that of the output load 101, and also being parallel with the output capacitor CL of load 101.
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the application, to combine the references as cited, so that fluctuation is minimized … (see para 0113 in Ito).
Allowable Subject Matter
Claims 2 – 14 and 16 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm.
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LY D. PHAM
Examiner
Art Unit 2827
/LY D PHAM/Primary Examiner, Art Unit 2827 July 7, 2026
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