DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1 and 20 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by Tang et al. (US Pat 9,436,197).
Regarding claims 1 and 20, Tang et al. disclose an electronic device (figs. 1 – 5 and all related texts) comprising:
a voltage regulator (mainly referred to as op amp 110 and pass device 120, fig. 1) configured to convert an input voltage (VAA, fig. 1) to generate an output voltage (Vreg, fig. 1) through an output node (at Vreg/Iload node, fig. 1);
a load device (referred to as RL as part of 101, fig. 1) configured to receive the output voltage (Vreg);
an output capacitor connected to the output node (referred to as CL), the output capacitor having a fixed capacitance (referred to as Load capacitance with fixed capacitance of the particular load device);
a capacitance controller (130, fig. 1) configured to generate a plurality of capacitance control signals based on a state signal indicating an operation state of the electronic device (output of 150 to Variable capacitance device 160 based on load current, see col. 2, lines 53 – 58); and
a variable capacitance circuit (160, fig. 1) connected to the output node (as shown at node Vreg in fig. 1), the variable capacitance circuit having a capacitance that changes based on the plurality of capacitance control signals (col. 4, lines 7 – 23).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kobayashi et (US Pat Pub 2022/0197520) in view of Potanin et al. (US Pat Pub 2015/0349631) (OR in view of Tang et al. in US Pat 9,436,197 as shown above).
Regarding claim 15, Kobayashi et al. disclose the storage device (for example fig. 1 and all related texts) comprising:
a nonvolatile memory device configured to store data (for example NAND memory 16, fig. 1, para 0027);
a storage controller configured to control the nonvolatile memory device (referred to as the NAND controller 38, see para 0038).
a voltage regulator (for example power supply circuit 22, fig. 2) configured to convert an input voltage (referred to as external power supply, fig. 2) to generate an output voltage (see all the outputs from circuit 22 in fig. 2), and configured to supply the output voltage to the nonvolatile memory device and the storage controller (referred to as the output to controller 18 and the outputs to NAND memory 16, fig. 2).
Kobayashi et al. disclose the storage device as shown above, except:
an output capacitor connected to the output node, the output capacitor having a fixed capacitance;
a capacitance controller configured to generate a plurality of capacitance control signals based on a state signal indicating an operation state of the electronic device; and
a variable capacitance circuit connected to the output node, the variable capacitance circuit having a capacitance that changes based on the plurality of capacitance control signals.
However, these features are taught by Potanin et al. (OR Tang et al. as shown above), (including the above-claimed “voltage regulator” limitation as follows):
a voltage regulator (“voltage regulator implemented as an IC may include a power transistor 104, para 0021, fig. 1) configured to convert an input voltage (Vin) to generate an output voltage (Vout) through an output node (referred to as the output node of power transistor 104 where Load device L and output capacitance CL is connected thereto, fig. 1);
an output capacitor connected to the output node (referred to as CL connected to the output node as shown in fig. 1), the output capacitor having a fixed capacitance (capacitance is fixed due to particular characteristic of load device 118);
a capacitance controller (referred to as error amplifier 106 and unity gain buffer 114, fig. 1, para 0023) configured to generate a plurality of capacitance control signals based on a state signal indicating an operation state of the electronic device (output of amp 106 and buffer 114, depending on the operation of the diagram 100 with respect to the connected load device 118); and
a variable capacitance circuit connected to the output node (referred to as Cc 120 and Cu 122, fig. 1) having a capacitance that changes based on the plurality of capacitance control signals (see para 0021, 0023 and 0030).
Therefore, it would have been obvious to one of ordinary skill in the art, before the effective filing date of the invention, to combine the features taught by the prior arts as cited, so that output power is consistent for variable applicable loads to the power supply circuit for optimized performance (see abstract in Potanin et al.)
Allowable Subject Matter
Claims 2 – 14 and 16 – 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The prior arts of record fail to teach or reasonably suggest the devices as set forth above, further comprising, in combination, the features and limitations additionally claimed at least in claims 2 – 6, 13 and 14 (with respect to claim 1) and claims 16 – 19 (with respect to claim 15).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. See additional cited references for related disclosures to the claimed invention.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to LY D PHAM whose telephone number is (571)272-1793. The examiner can normally be reached M-F: 8am-5pm.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Amir Zarabian can be reached at 571-272-1852. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
LY D. PHAM
Examiner
Art Unit 2827
/LY D PHAM/Primary Examiner, Art Unit 2827 March 11, 2026