DETAILED ACTION
Notice of AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending in the application.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file (JP2023-100906 Japan 06/20/2023).
Information Disclosure Statement
The information Disclosure Statement (IDS) Form PTO-1449, filed 06/18/2024, 06/24/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein was considered by the examiner.
Drawings
The drawings submitted on 06/18/2024. These drawings are review and accepted by the examiner.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The claims in this application are given their broadest reasonable interpretation using the plain meaning of the claim language in light of the specification as it would be understood by one of ordinary skill in the art. The broadest reasonable interpretation of a claim element (also commonly referred to as a claim limitation) is limited by the description in the specification when 35 U.S.C. 112(f) is invoked.
As explained in MPEP § 2181, subsection I, claim limitations that meet the following three-prong test will be interpreted under 35 U.S.C. 112(f):
(A) the claim limitation uses the term “means” or “step” or a term used as a substitute for “means” that is a generic placeholder (also called a nonce term or a non-structural term having no specific structural meaning) for performing the claimed function;
(B) the term “means” or “step” or the generic placeholder is modified by functional language, typically, but not always linked by the transition word “for” (e.g., “means for”) or another linking word or phrase, such as “configured to” or “so that”; and
(C) the term “means” or “step” or the generic placeholder is not modified by sufficient structure, material, or acts for performing the claimed function.
Use of the word “means” (or “step”) in a claim with functional language creates a rebuttable presumption that the claim limitation is to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites sufficient structure, material, or acts to entirely perform the recited function.
Absence of the word “means” (or “step”) in a claim creates a rebuttable presumption that the claim limitation is not to be treated in accordance with 35 U.S.C. 112(f). The presumption that the claim limitation is not interpreted under 35 U.S.C. 112(f) is rebutted when the claim limitation recites function without reciting sufficient structure, material or acts to entirely perform the recited function.
Claim limitations in this application that use the word “means” (or “step”) are being interpreted under 35 U.S.C. 112(f) except as otherwise indicated in an Office action. Conversely, claim limitations in this application that do not use the word “means” (or “step”) are not being interpreted under 35 U.S.C. 112(f), except as otherwise indicated in an Office action.
This application includes one or more claim limitations that use recite functional language but are not interpreted under 35 U.S.C. 112(f). Such claim limitation(s) is/are:
Apparatus claims 1-20’s “controller” that is “configured to” perform recited operations;
Because these claim limitation(s) are not being interpreted under 35 U.S.C. 112(f), they are not being interpreted to cover only the corresponding structure, material, or acts described in the specification as performing the claimed function, and equivalents thereof.
If applicant intends to have this/these limitation(s) interpreted under 35 U.S.C. 112(f), applicant may: (1) amend the claim limitation(s) to remove the structure, materials, or acts that performs the claimed function; or (2) present a sufficient showing that the claim limitation(s) does/do not recite sufficient structure, materials, or acts to perform the claimed function.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-20 are rejected under 35 U.S.C. 103 as being unpatentable over Sakurada (US 10,210,042 B2 hereinafter “Sakurada_1”) in view of Sakurada- (US 8,625,347 B2 hereinafter “Sakurada_2”).
Per MPEP 2111 and 2111.01, the claims are given their broadest reasonable interpretation and the words of the claims are given their plain meaning consistent with the specification without importing claim limitations from the specification.
Regarding Independent Claim 1, Sakurada, for example in Figs. 1-38, discloses a memory system (e.g., memory system 1; in Fig. 1 related in Figs. 2-38) comprising:
a semiconductor memory (e.g., NAND flash memory 10; in Fig. 1 related in Figs. 2-38) including a plurality of first memory cells each configured to store data in a non-volatile manner (within Memory cell array 110; in Fig. 2 related in Figs. 1, 3-38) according to a threshold voltage (e.g., the threshold voltages; in Figs. 3-5 related in Figs. 1-2, 6-38); and
a controller (e.g., Memory controller 20; in Fig. 1 related in Figs. 2-38), wherein
the controller is configured to perform a first error correction process for the plurality of first memory cells (via Error Correction code ECC 260; in Fig. 1 related in Figs. 2-38), based on first hard bit data (e.g., an Hard Bit read operation HB using the voltage AR(0) or S101; in Fig. 5-12, 15, 19 related in Figs. 1-4, 13-14, 16-18, 20-38) and first soft bit data acquired (e.g., Soft Bit as SB1/SB2; in Fig. 5-12, 15, 19 related in Figs. 1-4, 13-14, 16-18, 20-38) using a plurality of first soft bit voltages (e.g., voltage AR; in Fig. 5-12, 15, 19 related in Figs. 1-4, 13-14, 16-18, 20-38) that have been based on a shift voltage (e.g., the steps of S105-S106; in Fig. 12), and
the controller is configured to correct the shift voltage when a condition based on correction data generated during the first error correction process, is satisfied (e.g., the steps of S405-S406 or S605-S608; in Figs. 22, 24 related in Figs. 1-21, 23, 25-38).
However, Sakurada_1 is silent with regard to use the plurality of first soft bit voltages that have been calculated based on the shift voltage.
In the same field of endeavor, Sakurada_2, for example in Figs. 1-16, discloses the plurality of first soft bit voltages that have been calculated based on the shift voltage (e.g., the steps of S17/S34/; in Figs. 9, 12, 14 related in Figs. 1-8, 10-11, 13, 15-16).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Sakurada such as memory system (see for example in Figs. 1-38 of Sakurada_1) by incorporating the teaching of Sakurada_2 such as memory device and control method of memory device (see for example in Figs. 1-16 of Sakurada_2), for the purpose of controlling the applying voltages of a read voltage set including (2N-1) hard bit read voltages and a plurality of soft bit read voltages to each of the memory cells (Sakurada_2, Co. 3, lines 1-4).
The structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 2, the above Sakurada_1/Sakurada_2, combination discloses wherein the semiconductor memory further includes a plurality of second memory cells each configured to store data in a non-volatile manner according to a threshold voltage (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2), and the controller is configured to perform a second error correction process for the plurality of second memory cells, based on second hard bit data and second soft bit data acquired using a plurality of second soft bit voltages that have been calculated based on the corrected shift voltage (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2). Also, the structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 3, the above Sakurada_1/Sakurada_2, combination discloses wherein the first hard bit data is acquired using a first hard bit voltage that is greater than a first voltage having a lowest voltage among the plurality of first soft bit voltages (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2) and less than a second voltage having a highest voltage among the plurality of first soft bit voltages (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2). Also, the structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 4, the above Sakurada_1/Sakurada_2, combination discloses wherein the second hard bit data is acquired using a second hard bit voltage that is different from the first hard bit voltage (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2). Also, the structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 5, the above Sakurada_1/Sakurada_2, combination discloses wherein the controller is configured to correct the shift voltage when the first error correction process completes successfully (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2). Also, the structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 6, the above Sakurada_1/Sakurada_2, combination discloses wherein the controller calculates, based on a result of the first error correction process, a first quantity of first memory cells determined to store a first value (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2) and having a threshold voltage that is lower than a lowest voltage among the plurality of first soft bit voltages, and the condition is satisfied if the first quantity is one or more (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2). Also, the structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 7, the above Sakurada_1/Sakurada_2, combination discloses wherein the controller calculates, based on a result of the first error correction process (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2), a first quantity of first memory cells determined to store a second value and having a threshold voltage that is higher than a highest voltage among the plurality of first soft bit voltages (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2), and the condition is satisfied if the first quantity is one or more (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2). Also, the structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding Independent Claim 8, Sakurada_1, for example in Figs. 1-38, discloses a memory system (e.g., memory system 1; in Fig. 1 related in Figs. 2-38) comprising:
a semiconductor memory (e.g., NAND flash memory 10; in Fig. 1 related in Figs. 2-38) including a plurality of first memory cells each configured to store data in a non-volatile manner (within Memory cell array 110; in Fig. 2 related in Figs. 1, 3-38) according to a threshold voltage (e.g., the threshold voltages; in Figs. 3-5 related in Figs. 1-2, 6-38); and
a controller (e.g., Memory controller 20; in Fig. 1 related in Figs. 2-38), wherein
the controller is configured to perform a first error correction process for the plurality of first memory cells (via Error Correction code ECC 260; in Fig. 1 related in Figs. 2-38), based on first hard bit data that is acquired using a first hard bit voltage (e.g., an Hard Bit read operation HB using the voltage AR(0) or S101; in Fig. 5-12, 15, 19 related in Figs. 1-4, 13-14, 16-18, 20-38) and first soft bit data (e.g., Soft Bit SB1/SB2; in Fig. 5-12, 15, 19 related in Figs. 1-4, 13-14, 16-18, 20-38) acquired using a plurality of first soft bit voltages that are less than the first hard bit voltage (e.g., AR(-1)/AR(-2)/AR(-3); in Fig. 5-12, 15, 19 related in Figs. 1-4, 13-14, 16-18, 20-38), which have been based on a first shift voltage (e.g., voltage AR; in Fig. 5-12, 15, 19 related in Figs. 1-4, 13-14, 16-18, 20-38), and a plurality of second soft bit voltages that are greater than the first hard bit voltage (e.g., AR(+1)/AR(+2)/AR(+3); in Fig. 5-12, 15, 19 related in Figs. 1-4, 13-14, 16-18, 20-38), which have been based on a second shift voltage (e.g., voltage AR; in Fig. 5-12, 15, 19 related in Figs. 1-4, 13-14, 16-18, 20-38), and
the controller is configured to correct the first shift voltage when a first condition based on correction data generated during the first error correction process, is satisfied (e.g., the steps of S102/S104; in Figs. 5, 12, 15, 22, 24 related in Figs. 1-4, 6-11, 13-14, 16-21, 23, 25-38), and to correct the second shift voltage when a second condition based on the correction data generated during the first error correction process, is satisfied (see for example in Figs. 12, 15, 22-24, 29-30, 34, 37 related in Figs. 1-11, 13-14, 16-21, 25-28, 31-33, 35-36, 38).
However, Sakurada_1 is silent with regard to use the plurality of first soft bit voltages that have been calculated based on the shift voltage.
In the same field of endeavor, Sakurada_2, for example in Figs. 1-16, discloses the plurality of first soft bit voltages that have been calculated based on the shift voltage (e.g., the steps of S17/S34/; in Figs. 9, 12, 14 related in Figs. 1-8, 10-11, 13, 15-16).
It would have been obvious before the effective filling date of the claimed invention was made to a person having ordinary skill in the art to modify the teaching of Sakurada such as memory system (see for example in Figs. 1-38 of Sakurada_1) by incorporating the teaching of Sakurada_2 such as memory device and control method of memory device (see for example in Figs. 1-16 of Sakurada_2), for the purpose of controlling the applying voltages of a read voltage set including (2N-1) hard bit read voltages and a plurality of soft bit read voltages to each of the memory cells (Sakurada_2, Co. 3, lines 1-4).
The structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 9, the above Sakurada_1/Sakurada_2, combination discloses wherein each of the first soft bit voltages is less than the hard bit voltage by an integer multiple of the first shift voltage (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2), and each of the second soft bit voltages is greater than the hard bit voltage by an integer multiple of the second shift voltage (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2). Also, the structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 10, the above Sakurada_1/Sakurada_2, combination discloses wherein the corrected first shift voltage is larger than the first shift voltage (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2), and the corrected second shift voltage is larger than the second shift voltage (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2). Also, the structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 11, the above Sakurada_1/Sakurada_2, combination discloses wherein the controller is configured to correct the first shift voltage and the second shift voltage (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2), when the first error correction process completes successfully (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2). Also, the structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 12, the above Sakurada_1/Sakurada_2, combination discloses wherein the controller calculates, based on a result of the first error correction process, a first quantity of first memory cells determined to store a first value and having a threshold voltage that is lower than a lowest voltage among the plurality of first soft bit voltages (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2), a second quantity of first memory cells determined to store a second value and having a threshold voltage that is higher than a highest voltage among the plurality of second soft bit voltages (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2), and the first condition is satisfied when the first quantity is one or more, and the second condition is satisfied when the second quantity is one or more(see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2). Also, the structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 13, the above Sakurada_1/Sakurada_2, combination discloses wherein the first condition is satisfied when the first quantity is equal to or more than a first reference quantity, and the second condition satisfied when the second quantity is equal to or more than a second reference quantity (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2). Also, the structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 14, the above Sakurada_1/Sakurada_2, combination discloses wherein the controller is configured to correct the first shift voltage based on a quantity of first memory cells determined to store the first value in each of a plurality of threshold voltage ranges that are defined by the first soft bit voltages (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2), the hard bit voltage, and the second soft bit voltages between the lowest voltage among the plurality of first soft bit voltages and the highest voltage among the plurality of second soft bit voltages (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2), and the controller is configured to correct the second shift voltage based on a quantity of first memory cells determined to store the second value in each of the plurality of threshold voltage ranges (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2). Also, the structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 15, the above Sakurada_1/Sakurada_2, combination discloses wherein the controller is configured to correct the first shift voltage such that a quantity of first memory cells determined to store the first value and having a threshold value that is less than a lowest of a plurality of third soft bit voltages that are calculated using the corrected first shift voltage is zero (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2), and the controller is configured to correct the second shift voltage such that a quantity of first memory cells determined to store the second value and having a threshold value that is greater than a highest of a plurality of fourth soft bit voltages that are calculated using the corrected second shift voltage is zero (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2). Also, the structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 16, the above Sakurada_1/Sakurada_2, combination discloses wherein the controller calculates, based on a result of the first error correction process, a first quantity of first memory cells determined to store a first value and having a threshold voltage that is lower than a lowest voltage among the plurality of first soft bit voltages (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2), a second quantity of first memory cells determined to store a second value and having a threshold voltage that is higher than a highest voltage among the plurality of second soft bit voltages (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2), and the first condition is satisfied when a first proportion for the first quantity is equal to or greater than a first reference proportion, and the second condition is satisfied when a second proportion for the second quantity is equal to or greater than a second reference proportion (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2). Also, the structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 17, the above Sakurada_1/Sakurada_2, combination discloses wherein the first proportion is a proportion of the first quantity to a quantity of first memory cells determined to store the first value and having a threshold voltage that is lower than the first hard bit voltage (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2), and the second proportion is a proportion of the second quantity to a quantity of first memory cells determined to store the second value and having a threshold voltage is equal to or higher than the first hard bit voltage (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2). Also, the structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 18, the above Sakurada_1/Sakurada_2, combination discloses wherein the controller is configured to correct the first shift voltage according to a magnitude of the first proportion, and the controller is configured to correct the second shift voltage according to a magnitude of the second proportion (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2). Also, the structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 19, the above Sakurada_1/Sakurada_2, combination discloses wherein the controller is configured to calculate at least one of a third shift voltage that is different from the first shift voltage and the corrected first shift voltage, and a fourth shift voltage that is different from the second shift voltage and the corrected second shift voltage (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2), when the first error correction process does not complete successfully, and the controller is configured to perform a second error correction process for the plurality of first memory cells, based on second hard bit data that is acquired using a second hard bit voltage that is different from the first hard bit voltage and second soft bit data acquired using a plurality of third soft bit voltages (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2), which have been calculated based on at least one the third shift voltage and the fourth shift voltage (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2). Also, the structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Regarding claim 20, the above Sakurada_1/Sakurada_2, combination discloses wherein the semiconductor memory further includes a first word line connected to the plurality of first memory cells, and a plurality of second memory cells each configured to store data in a non-volatile manner according to a threshold voltage and connected to the first word line together with the plurality of first memory cells (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2), and the first hard bit data and the first soft bit data each include data for the first memory cells and data for the second memory cells (see for example in Figs. 1-38 of Sakurada_1 and also see in Figs. 1-16 of Sakurada_2). Also, the structure in of the prior art (Sakurada_1 and Sakurada_2) is substantially identical to the structure of the claims. MPEP 2112.01(I). The manner of operation does not distinguish this apparatus claim from the prior art apparatus. MPEP 2114(II).
Conclusion
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/THA-O H BUI/Primary Examiner, Art Unit 2825 12/13/2025