DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2, 5-15, 17-18, and 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Fan et al. (U.S. Patent No. 10,644,011).
Regarding to claim 1, Fan teaches a non-volatile memory device, comprising at least one memory cell, wherein the at least one memory cell comprises:
a substrate (Fig. 1C, element 100);
a select gate disposed on the substrate (Fig. 1C, element 106; column 6, line 8);
a control gate disposed on the substrate and laterally spaced apart from the select gate (Fig. 1C, element 112; column 5, line 64);
an erase gate disposed on the substrate and laterally spaced apart from the control gate (Fig. 1C, element 110; column 6, lines 25-26), wherein the erase gate comprises a concave corner (Fig. 1C, near corner 126); and
a floating gate covered with the control gate and the erase gate (Fig. 1C, element 108; column 6, line 19), wherein the floating gate comprises a convex corner (Fig. 1C, element 126),
wherein the convex corner of the floating gate faces the concave corner of the erase gate (Fig. 1C);
wherein a vertex of the convex corner of the floating gate is lower than a top surface of the select gate (Fig. 1C, vertex 126 of the floating gate 108 is lower than a top surface of the select gate 106).
Regarding to claim 2, Fan teaches the convex corner of the floating gate points toward the concave corner of the erase gate (Fig. 1C).
Regarding to claim 5, Fan teaches the floating gate further comprises:
a base portion (Fig. 1C, center portion of 108); and
a protruding portion disposed on a top surface or a sidewall of the base portion (Fig. 1C, up-right portion of 108, or up-left portion of 108),
wherein the base portion extends from below the control gate to below the erase gate (Fig. 1C).
Regarding to claim 6, Fan teaches the protruding portion is laterally spaced apart from the control gate (Fig. 1C).
Regarding to claim 7, Fan teaches the protruding portion comprises the convex corner (Fig. 1C).
Regarding to claim 8, Fan teaches a portion of the erase gate is laterally spaced apart from the base portion (Fig. 1C).
Regarding to claim 9, Fan teaches the erase gate is disposed on the protruding portion and laterally spaced apart from the select gate (Fig. 1C).
Regarding to claim 10, Fan teaches the base portion comprises the convex corner (Fig. 1C).
Regarding to claim 11, Fan teaches the protruding portion extends from the base portion toward the select gate (Fig. 1C, the protruding portion extends from the base portion toward the select gate 106).
Regarding to claim 12, Fan teaches a thickness of the protruding portion is less than a thickness of the base portion (Fig. 1C, lateral thickness of the protruding portion is less than a thickness of the base portion).
Regarding to claim 13, Fan teaches the erase gate further comprises:
a base portion (Fig. 1C, upper portion of 110); and
a protruding portion disposed under the base portion (Fig. 1C, lower portion of 110),
wherein a bottom surface of the protruding portion is lower than a bottom surface of the base portion (Fig. 1C).
Regarding to claim 14, Fan teaches the bottom surface of the protruding portion of the erase gate is lower than the vertex of the convex corner of the floating gate (Fig. 1C).
Regarding to claim 15, Fan teaches the protruding portion of the erase gate is laterally spaced apart from the floating gate (Fig. 1C).
Regarding to claim 17, Fan teaches the protruding portion of the erase gate is laterally spaced apart from the select gate (Fig. 1C).
Regarding to claim 18, Fan teaches a coupling dielectric layer disposed on the substrate (Fig. 1C, element 122), wherein the coupling dielectric layer comprises:
a first portion disposed between the control gate and the floating gate (Fig. 1C, first portion disposed between the control gate 112 and the floating gate 108); and
a second portion disposed between the control gate and the erase gate, wherein a top surface of the second portion is level with a top surface of the erase gate (Fig. 1C).
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Regarding to claim 20, Fan teaches the at least one memory cell comprises a first memory cell and a second memory cell (Fig. 1A, column 5, lines 36-41), each of the first memory cell and the second memory cell comprises the select gate (Fig. 1C, element 106), the control gate (Fig. 1C, element 112), the erase gate (Fig. 1C, element 110) and the floating gate (Fig. 1C, element 108), and the non-volatile memory device further comprises a source region (Fig. 1C, element 102) shared by the first memory cell and the second memory cell (Fig. 1A-C), wherein the source region and the erase gate extend along a same direction (Fig. 1C).
Claims 1-4, 13-15, and 17-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsair et al. (U.S. Patent No. 8,890,232).
Regarding to claim 1, Tsair teaches a non-volatile memory device, comprising at least one memory cell, wherein the at least one memory cell comprises:
a substrate (Fig. 1, element 13);
a select gate disposed on the substrate (Fig. 1, element 49);
a control gate disposed on the substrate and laterally spaced apart from the select gate (Fig. 1, element 23);
an erase gate disposed on the substrate and laterally spaced apart from the control gate (Fig. 1, element 47), wherein the erase gate comprises a concave corner (Fig. 1, corner 40); and
a floating gate covered with the control gate and the erase gate (Fig. 1, element 17), wherein the floating gate comprises a convex corner (Fig. 1, corner 40),
wherein the convex corner of the floating gate faces the concave corner of the erase gate (Fig. 1);
wherein a vertex of the convex corner of the floating gate is lower than a top surface of the select gate (Fig. 1, vertex of the floating gate 17 is lower than a top surface of the select gate 49).
Regarding to claim 2, Tsair teaches the convex corner of the floating gate points toward the concave corner of the erase gate (Fig. 1).
Regarding to claim 3, Tsair teaches a top surface of the erase gate is level with a top surface of the control gate (Fig. 1, top surface of the erase gate 47 is level with top surface of the control gate 23).
Regarding to claim 4, Tsair teaches a top surface of the erase gate, a top surface of the control gate, and a top surface of the select gate are level with each other (Fig. 1, top surface of the erase gate 47, top surface of the control gate 23, and top surface of the select gate 49 are level with each other).
Regarding to claim 13, Tsair teaches the erase gate further comprises:
a base portion (Fig. 1, upper portion of 47); and
a protruding portion disposed under the base portion (Fig. 1, lower portion of 47),
wherein a bottom surface of the protruding portion is lower than a bottom surface of the base portion (Fig. 1).
Regarding to claim 14, Tsair teaches the bottom surface of the protruding portion of the erase gate is lower than the vertex of the convex corner of the floating gate (Fig. 1).
Regarding to claim 15, Tsair teaches the protruding portion of the erase gate is laterally spaced apart from the floating gate (Fig. 1).
Regarding to claim 17, Tsair teaches the protruding portion of the erase gate is laterally spaced apart from the select gate (Fig. 1).
Regarding to claim 18, Tsair teaches coupling dielectric layer disposed on the substrate (column 2, lines 45-49), wherein the coupling dielectric layer comprises:
a first portion disposed between the control gate and the floating gate (Fig. 1); and
a second portion disposed between the control gate and the erase gate, wherein a top surface of the second portion is level with a top surface of the erase gate (Fig. 1).
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Regarding to claim 19, Tsair teaches the top surface of the second portion is level with a top surface of the control gate and a top surface of the select gate (Fig. 1).
Regarding to claim 20, Tsair teaches the at least one memory cell comprises a first memory cell and a second memory cell (Fig. 2), each of the first memory cell and the second memory cell comprises the select gate, the control gate, the erase gate and the floating gate, and the non-volatile memory device further comprises a source region shared by the first memory cell and the second memory cell, wherein the source region and the erase gate extend along a same direction (Fig. 1).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 3-4 are rejected under 35 U.S.C. 103 as being unpatentable over Fan et al. (U.S. Patent No. 10,644,011), as applied to claim 1 above, in view of Lin et al. (U.S. Patent No. 12,317,488).
Regarding to claim 3, Fan does not explicitly disclose a top surface of the erase gate is level with a top surface of the control gate.
Lin discloses a top surface of the erase gate is level with a top surface of the control gate (Fig. 1, a top surface of the erase gate 134 is level with a top surface of the control gate 121). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fan in view of Lin to configure a top surface of the erase gate to be level with a top surface of the control gate in order to simply the fabrication process, thus to reduce manufacturing cost.
Regarding to claim 4, Fan does not explicitly disclose a top surface of the erase gate, a top surface of the control gate, and a top surface of the select gate are level with each other.
Lin discloses a top surface of the erase gate, a top surface of the control gate, and a top surface of the select gate are level with each other (Fig. 1, a top surface of the erase gate 134, a top surface of the control gate 121, and a top surface of the select gate 128 are level with each other). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fan in view of Lin to configure a top surface of the erase gate, a top surface of the control gate, and a top surface of the select gate to be level with each other, in order to simply the fabrication process, thus to reduce manufacturing cost.
Claim 16 is rejected under 35 U.S.C. 103 as being unpatentable over Fan et al. (U.S. Patent No. 10,644,011), as applied to claim 1 and claim 13 above, in view of Wang et al. (U.S. Patent No. 11,316,024).
Regarding to claim 16, Fan does not explicitly disclose a portion of the select gate is disposed between the protruding portion of the erase gate and the substrate.
Wang discloses a portion of a select gate is disposed between a protruding portion of erase gate and a substrate (Fig. 6, portion of the select gate 34a is disposed between the protruding portion of the erase gate 38a and the substrate 10). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fan in view of Wang to dispose a portion of the select gate between the protruding portion of the erase gate and the substrate in order to increase sensitivity.
Claim 19 is rejected under 35 U.S.C. 103 as being unpatentable over Fan et al. (U.S. Patent No. 10,644,011), as applied to claim 1 and claim 18 above, in view of Lin et al. (U.S. Patent No. 12,317,488).
Regarding to claim 19, Fan does not explicitly disclose the top surface of the second portion is level with a top surface of the control gate and a top surface of the select gate.
Lin discloses the top surface of the second portion of the dielectric layer is level with a top surface of the control gate and a top surface of the select gate (Fig. 1, the top surface of the second portion of the dielectric layer 148 is level with a top surface of the control gate 121 and a top surface of the select gate 128). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fan in view of Lin to configure the top surface of the second portion to be level with a top surface of the control gate and a top surface of the select gate, in order to simply the fabrication process, thus to reduce manufacturing cost.
Pertinent Art
For the benefits of the Applicant, US-9583640-B1, US-9548312-B1, US-10714489-B2, US-11507816-B2, US-12641783-B2, US-11849577-B2, and US-10312248-B2, are cited on the record as being pertinent to significant disclosure through some but not all claimed features of the defined invention. These references fail to disclose a portion of the select gate is disposed between the protruding portion of the erase gate and the substrate.
Conclusion
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/VU A VU/Primary Examiner, Art Unit 2897
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