Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/18/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-3, 9-12 and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2020/0409859 (“Saleh et al.”) in view of US Patent No. 9,398,123 (“Vermani et al.”).
Regarding claim 1, Saleh et al. discloses a graphics processor (Fig. 1, GPU) comprising:
a first semiconductor die (fig. 1, GPU chiplet 106-2) including a first control path circuit or processor that determines a first monitoring parameter and sends a forwarding command packet indicating the first monitoring parameter to a second semiconductor die (fig. 1, GPU chiplet 106-1) (requested data is sent from the second chiplet to the first chiplet [0030] The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink).
Saleh et al. discloses request a first monitoring parameter but does not specify the second semiconductor die including a second control path circuit or processor that determines a second monitoring parameter and determines a global monitoring parameter in response to the forwarding command packet and the determined second monitoring parameter.
In a similar field of endeavor, Vermani et al. discloses distributed temporal correlation among a plurality of devices as illustrated and described with respect to FIG. 5D A first sub-band 515a modulates data for a single device (“Device 1”) for the duration of the high efficiency payload field 514c. Similarly, sub-band 515c also modulates data for a single device (“Device 3”) for the duration of the high efficiency payload field 514c. Sub-band 515b modulates data for two different devices (“Device 2A” and “Device 2B”). Data for multiple devices may be transmitted within a single sub-band, as shown in FIG. 5D, by overloading a group identifier for two devices. For example, if two devices have the same user position within a group id that is signaled in the signal field 512c. For example, as shown in FIG. 5D, device 2A and device 2B may have the same position within a GID signaled by the signal field 512c.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the multi-chip GPU architecture of Saleh et al. to apply Vermani’s temporal correlation techniques in order to improve performance analysis by permitting temporally related activity occurring on different GPU chiplets to be analyzed together rather an independently.
Regarding claim 2, Saleh et al. in view of Vermani et al. discloses the graphics processor of claim 1 wherein the first and second monitoring parameters are each temporal (Vermani, the monitored parameter is duration which corresponds to temporal).
Regarding claim 3, Saleh et al. discloses a method comprising:
determining a first monitored parameter local to a first semiconductor die (fig. 1, GPU chiplet 106-2); determining a second monitored parameter local to a second semiconductor die (fig. 1, GPU chiplet 106-1); forwarding information indicating the first monitored parameter from the first semiconductor die to the second semiconductor die (requested data is sent from the second chiplet to the first chiplet [0030] The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink).
Saleh et al. discloses request a first monitored parameter but does not specify the monitored parameter being a temporal region of interest and determining a global temporal region of interest in response to the forwarded information and the determined second temporal region of interest.
In a similar field of endeavor, Vermani et al. discloses distributed temporal correlation among a plurality of devices as illustrated and described with respect to FIG. 5D A first sub-band 515a modulates data for a single device (“Device 1”) for the duration of the high efficiency payload field 514c. Similarly, sub-band 515c also modulates data for a single device (“Device 3”) for the duration of the high efficiency payload field 514c. Sub-band 515b modulates data for two different devices (“Device 2A” and “Device 2B”). Data for multiple devices may be transmitted within a single sub-band, as shown in FIG. 5D, by overloading a group identifier for two devices. For example, if two devices have the same user position within a group id that is signaled in the signal field 512c. For example, as shown in FIG. 5D, device 2A and device 2B may have the same position within a GID signaled by the signal field 512c. The monitoring parameters in Vermani is duration which corresponds to the claimed temporal region of interest.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the multi-chip GPU architecture of Saleh et al. to apply Vermani’s temporal correlation techniques in order to improve performance analysis by permitting temporally related activity occurring on different GPU chiplets to be analyzed together rather an independently.
Regarding claim 12, Saleh et al. discloses a processing system comprising:
a first semiconductor die (fig. 1, GPU chiplet 106-2) including a first control path circuit or processor that determines a first monitored parameter local to the first die and forwards information indicating the first monitored parameter to a second semiconductor die (fig. 1, GPU chiplet 106-1); and the second semiconductor die including a second control path circuit or processor that determines a second temporal region of interest local to the second semiconductor die (requested data is sent from the second chiplet to the first chiplet [0030] The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink).
Saleh et al. discloses request a first monitored parameter but does not specify the monitored parameter being a temporal region of interest and determines a global temporal region of interest in response to the forwarded information and the determined second temporal region of interest.
In a similar field of endeavor, Vermani et al. discloses distributed temporal correlation among a plurality of devices as illustrated and described with respect to FIG. 5D A first sub-band 515a modulates data for a single device (“Device 1”) for the duration of the high efficiency payload field 514c. Similarly, sub-band 515c also modulates data for a single device (“Device 3”) for the duration of the high efficiency payload field 514c. Sub-band 515b modulates data for two different devices (“Device 2A” and “Device 2B”). Data for multiple devices may be transmitted within a single sub-band, as shown in FIG. 5D, by overloading a group identifier for two devices. For example, if two devices have the same user position within a group id that is signaled in the signal field 512c. For example, as shown in FIG. 5D, device 2A and device 2B may have the same position within a GID signaled by the signal field 512c. The monitoring parameters in Vermani is duration which corresponds to the claimed temporal region of interest.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the multi-chip GPU architecture of Saleh et al. to apply Vermani’s temporal correlation techniques in order to improve performance analysis by permitting temporally related activity occurring on different GPU chiplets to be analyzed together rather an independently.
Regarding claims 9 and 18, the above combination discloses the method of claim 3 wherein determining the global temporal region of interest comprises selecting the global temporal region of interest relative to the first temporal region of interest and the second temporal region of interest (Vermani, Data for multiple devices may be correlated to form a global temporal region of interest, as shown in FIG. 5D, by overloading a group identifier for two devices. For example, if two devices have the same user position within a group id that is signaled in the signal field 512c (corresponding to payload 514c)).
Regarding claims 10 and 19, the above combination discloses the method of claim 3 further including triggering to snapshot performance data or propagating command and control information to a first data generator on the first semiconductor die during the global temporal region of interest, and triggering to snapshot performance data or propagating command and control information to a second data generator on the second semiconductor die during the global temporal region of interest (Saleh, the primary GPU chiplet 106-1 makes a data request [0030] The passive crosslink controller 404 determines that data associated with memory address XYZ is cached in L3 cache memory 310 of secondary GPU chiplet 106-4. Based on that determination, the access request is routed via signal route 506 of the passive crosslink 118 to secondary GPU chiplet 106-4. The secondary GPU chiplet 106-4 returns the result back to primary GPU chiplet 106-1, which subsequently returns the requested data to the originating requestor (i.e., CPU 102). In this manner, the CPU 102 only has a single external view and does not require direct communications to two or more GPU chiplets 106 via bus 108).
Regarding claim 11 and 20, the above combination discloses the method of claim 10 wherein at least one of the first data generator and the second data generator comprises a performance data monitor (Chayat, telemetry performance data)
Claims 4 and 13 are rejected under 35 U.S.C. 103 as being unpatentable over US Publication No. 2020/0409859 (“Saleh et al.”) in view of US Patent No. 9,398,123 (“Vermani et al.”) and further in view of US Patent No. 10,433,035 (“Chayat et al.”).
Regarding claims 4 and 13, Saleh et al. in view of Vermani et al. discloses determining timing related event information associated with a monitored activity but does not specify wherein determining the first temporal region of interest is based on an engine start command and an engine stop command, the engine disposed on the first semiconductor die.
In the same field of endeavor, Chayat et al. discloses collecting telemetry data. A telemetry profile may be triggered by a specified trigger condition, and may read multiple telemetry values from a set of telemetry registers. The multiple telemetry data values may be included in a container. The container may be encapsulated according to a message profile to generate a telemetry message (col. 2, lines 1-19).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the monitoring system of Vermani et al. to incorporate the telemetry engine of Chayat et al. to provide more detailed performance monitoring enabling coordinated collection by initiating and terminating telemetry collection across the distributed GPU chiplets.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim 21 is rejected under 35 U.S.C. 102(a)(2) as being anticipated by US Publication No. 2020/0409859 (“Saleh et al.”).
Regarding claim 21, Saleh discloses a GPU (fig. 1, GPU) comprising:
a first semiconductor die (fig. 1, GPU chiplet 106-2) including a first control path circuit or processor that determines a first monitoring parameter and sends a forwarding command packet indicating the first monitoring parameter to a second semiconductor die
a first virtualizer that enables a first tenant to use first fractional parts of a first die and a second die, and enables a second tenant to use second fractional parts of the first die and the second die, wherein at least some of the first fractional parts are distinct from the second fractional parts (a physical GPU is logically divided into multiple virtual GPU instances- Fig. 1, 104);
a controller (fig. 1, CPU) that enables the first tenant to issue first performance monitoring commands for the first fractional parts and enables the second tenant to issue second performance monitoring commands for the second fractional parts (fig. 1, GPU chiplet 106-1); and
communication paths on the first die and the second die that keep the first monitoring commands and the second monitoring commands separate while communicating the first monitoring commands to the first fractional parts on the first die and the second die and communicating the second monitoring commands to the second fractional parts on the first die and the second die (requested data is sent from the second chiplet to the first chiplet [0030] The GPU chiplet array includes the first GPU chiplet communicably coupled to the CPU via a bus and a second GPU chiplet communicably coupled to the first GPU chiplet via a passive crosslink).
Allowable Subject Matter
Claims 5-8 and 14-17 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
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/JIRAPON TULOP/Examiner, Art Unit 2693
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