DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 1/13/2025 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-2, 6, 9-10, 16 and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Nam (US 2021/0159178).
Regarding claim 1, Nam discloses, in at least figure 1 and related text, a semiconductor packaging structure, comprising:
a first semiconductor chip (C0, [18], [21]);
wherein first-contact-pads (540, [20]) are formed on a surface of the first semiconductor chip (C0, [18], [21]);
a dielectric layer (150, [48]) located on the first semiconductor chip (C0, [18], [21]);
wherein second-contact-pads (160, [18]) are formed within the dielectric layer (150, [48]);
a second semiconductor chip stacking structure (C1/C2/C3, [18]) located on the dielectric layer (150, [48]);
wherein the second semiconductor chip stacking structure (C1/C2/C3, [18]) comprises a plurality of layers (110/210/210/310, [32], [42], [44]) of second semiconductor chips (C1/C2/C3, [18]) stacked in sequence; and
third-contact-pads (120, [32]) are formed on a surface of a first layer (110, [32]) of the plurality of layers (110/210/210/310, [32], [42], [44]) of the second semiconductor chips (C1/C2/C3, [18]); and
the first semiconductor chip (C0, [18], [21]) and the first layer (110, [32]) of the plurality of layers (110/210/210/310, [32], [42], [44]) of the second semiconductor chips (C1/C2/C3, [18]) are bonded to each other in an one-to-one correspondence manner through the first-contact-pads (540, [20]), the second-contact-pads (160, [18]) and the third-contact-pads (120, [32]); and, wherein,
a width of each of the second-contact-pads (160, [18]) is inconsistent with a width of each of corresponding first-contact-pads (540, [20]) or a width of each of corresponding third-contact-pads (120, [32]).
Regarding claim 2, Nam discloses the semiconductor packaging structure according to claim 1 as described above.
Nam further discloses, in at least figure 1 and related text, a width of each of the first-contact-pads (540, [20]) is consistent with a width of each of corresponding third-contact-pads (120, [32]).
Regarding claim 6, Nam discloses the semiconductor packaging structure according to claim 1 as described above.
Nam further discloses, in at least figure 1 and related text, a material of the dielectric layer (150, [48]) comprises a silicon-containing compound.
Regarding claim 9, Nam discloses, in at least figures 1, 11-12, and related text, a method for forming a semiconductor packaging structure, comprising:
forming a first semiconductor chip (C0, [18], [21]); and forming first-contact-pads (540, [20]) on a surface of the first semiconductor chip (C0, [18], [21]);
forming a dielectric layer (150, [48]) on the first semiconductor chip (C0, [18], [21]); and forming second-contact-pads (160, [18]) within the dielectric layer (150, [48]);
forming a second semiconductor chip stacking structure (C1/C2/C3, [18]) on the dielectric layer (150, [48]); wherein the second semiconductor chip stacking structure (C1/C2/C3, [18]) comprises a plurality of layers (110/210/210/310, [32], [42], [44]) of second semiconductor chips (C1/C2/C3, [18]) stacked in sequence; and forming third-contact-pads (120, [32]) on a surface of a first layer (110, [32]) of the plurality of layers (110/210/210/310, [32], [42], [44]) of the second semiconductor chips (C1/C2/C3, [18]); and
bonding the first semiconductor chip (C0, [18], [21]) and the first layer (110, [32]) of the plurality of layers (110/210/210/310, [32], [42], [44]) of the second semiconductor chips (C1/C2/C3, [18]) in an one-to-one correspondence manner through the first-contact-pads (540, [20]), the second-contact-pads (160, [18]) and the third-contact-pads (120, [32]); and, wherein,
a width of each of the second-contact-pads (160, [18]) is inconsistent with a width of each of corresponding first-contact-pads (540, [20]) or a width of each of corresponding third-contact-pads (120, [32]).
Regarding claim 10, Nam discloses the method according to claim 9 as described above.
Nam further discloses, in at least figures 1, 11-12, and related text, a width of each of the first-contact-pads (540, [20]) is consistent with a width of each of corresponding third-contact-pads (120, [32]).
Regarding claim 16, Nam discloses, in at least figure 1 and related text, a semiconductor packaging structure, comprising:
a first semiconductor chip (C0, [18], [21]); wherein first-contact-pads (540, [20]) are formed on a surface of the first semiconductor chip (C0, [18], [21]);
a dielectric layer (150, [48]) located on the first semiconductor chip (C0, [18], [21]); wherein second-contact-pads (160, [18]) are formed within the dielectric layer (150, [48]);
a second semiconductor chip stacking structure (C1/C2/C3, [18]) located on the dielectric layer (150, [48]); wherein the second semiconductor chip stacking structure (C1/C2/C3, [18]) comprises a plurality of layers (110/210/210/310, [32], [42], [44]) of second semiconductor chips (C1/C2/C3, [18]) stacked in sequence; and third-contact-pads (120, [32]) are formed on a surface of a first layer (110, [32]) of the plurality of layers (110/210/210/310, [32], [42], [44]) of the second semiconductor chips (C1/C2/C3, [18]); and
the first semiconductor chip (C0, [18], [21]) and the first layer (110, [32]) of the plurality of layers (110/210/210/310, [32], [42], [44]) of the second semiconductor chips (C1/C2/C3, [18]) are bonded to each other in an one-to-one correspondence manner through the first-contact-pads (540, [20]), the second-contact-pads (160, [18]) and the third-contact-pads (120, [32]); and, wherein,
a width of each of the second-contact-pads (160, [18]) is inconsistent with a width of each of corresponding first-contact-pads (540, [20]) and a width of each of corresponding third-contact-pads (120, [32]).
Regarding claim 20, Nam discloses the method according to claim 9 as described above.
Nam further discloses, in at least figures 1, 11-12, and related text, the width of each of the second-contact-pads (160, [18]) is inconsistent with the width of each of corresponding first-contact-pads (540, [20]) and the width of each of corresponding third-contact-pads (120, [32]).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 3 and 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nam (US 2021/0159178) in view of Huang (US 2023/0025094).
Regarding claim 3, Nam discloses the semiconductor packaging structure according to claim 1 as described above.
Nam does not explicitly disclose the first-contact-pads are formed on an active surface of the first semiconductor chip, and the third-contact-pads are formed on an active surface of the first layer of the plurality of layers of the second semiconductor chips, and the active surface of the first semiconductor chip is bonded to the active surface of the first layer of the plurality of layers of the second semiconductor chips; the active surface is a surface of a chip on which a device layer is formed.
Huang teaches, in at least figure 5 and related text, the device comprising the first-contact-pads (118/a/118b, [15]) are formed on an active surface of the first semiconductor chip (100, [14]), and the third-contact-pads (218/a/218b, [30]) are formed on an active surface of the first layer of the plurality of layers of the second semiconductor chips (200, [29]), and the active surface of the first semiconductor chip (100, [14]) is bonded to the active surface of the first layer of the plurality of layers of the second semiconductor chips (200, [29]); the active surface is a surface of a chip on which a device layer is formed ([14], [30], figure), for the purpose of providing improvement in integration density ([2]).
Nam and Huang are analogous art because they both are directed to semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Nam with the specified features of Huang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the structure disclosed in Nam to have the first-contact-pads being formed on an active surface of the first semiconductor chip, and the third-contact-pads being formed on an active surface of the first layer of the plurality of layers of the second semiconductor chips, and the active surface of the first semiconductor chip being bonded to the active surface of the first layer of the plurality of layers of the second semiconductor chips; the active surface being a surface of a chip on which a device layer is formed, as taught by Huang, for the purpose of providing improvement in integration density ([2], Huang).
Regarding claim 11, Nam discloses the method according to claim 9 as described above.
Nam does not explicitly disclose forming the first-contact-pads on an active surface of the first semiconductor chip; forming the third-contact-pads on an active surface of the first layer of the plurality of layers of the second semiconductor chips; bonding the active surface of the first semiconductor chip and the active surface of the first layer of the plurality of layers of the second semiconductor chips; the active surface is a surface of a chip on which a device layer is formed.
Huang teaches, in at least figure 5 and related text, the method comprising forming the first-contact-pads (118/a/118b, [15]) on an active surface of the first semiconductor chip (100, [14]); forming the third-contact-pads (218/a/218b, [30]) on an active surface of the first layer of the plurality of layers of the second semiconductor chips (200, [29]); bonding the active surface of the first semiconductor chip (100, [14]) and the active surface of the first layer of the plurality of layers of the second semiconductor chips (200, [29]); the active surface is a surface of a chip on which a device layer is formed ([14], [30], figure), for the purpose of providing improvement in integration density ([2]).
Nam and Huang are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Nam with the specified features of Huang because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Nam to have the forming the first-contact-pads on an active surface of the first semiconductor chip; the forming the third-contact-pads on an active surface of the first layer of the plurality of layers of the second semiconductor chips; the bonding the active surface of the first semiconductor chip and the active surface of the first layer of the plurality of layers of the second semiconductor chips; the active surface being a surface of a chip on which a device layer is formed, as taught by Huang, for the purpose of providing improvement in integration density ([2], Huang).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Nam (US 2021/0159178) in view of Kim (US 2021/0066251).
Regarding claim 12, Nam discloses the method according to claim 9 as described above.
Nam further discloses, in at least figure 1 and related text, a material of the dielectric layer (150, [48]) comprises a silicon-containing compound.
Nam does not explicitly disclose forming the dielectric layer on the first semiconductor chip by spin coating.
Kim teaches, in at least figures 4, 5, and related text, the method comprising forming the dielectric layer (140, [105]) on the first semiconductor chip (C1, [38]) by spin coating ([105]), for the purpose of providing a semiconductor package having improved reliability ([6]).
Nam and Kim are analogous art because they both are directed to method for forming a semiconductor device and one of ordinary skill in the art would have had a reasonable expectation of success to modify Nam with the specified features of Kim because they are from the same field of endeavor.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified the method disclosed in Nam to have the forming the dielectric layer on the first semiconductor chip by spin coating, as taught by Kim, for the purpose of providing a semiconductor package having improved reliability ([6], Kim).
Allowable Subject Matter
Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 4 that recite "widths of the first-contact-pads are inconsistent; widths of the second-contact-pads are inconsistent; widths of the third-contact-pads are inconsistent" in combination with other elements of the base claims 1 and 4.
Claim 5 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 5 that recite "the width of the first second-contact-pad is larger than a width of the first first-contact-pad or the first third-contact-pad corresponded thereto; the width of the second second-contact-pad is smaller than a width of the second first-contact-pad or the second third-contact-pad corresponded thereto" in combination with other elements of the base claims 1 and 5.
Claim 7 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 7 that recite "widths of corresponding fourth-contact-pads between adjacent two layers of the multiple layers of the plurality of layers of the second semiconductor chips are inconsistent" in combination with other elements of the base claims 1 and 7.
Claim 8 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 8 that recite "insulating layers located between sidewalls of the second-contact-pads and the dielectric layer; Young’s modulus of the insulating layers is smaller than Young’s modulus of the dielectric layer" in combination with other elements of the base claims 1 and 8.
Claim 13 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 9 and 13 that recite "widths of corresponding fourth-contact-pads between adjacent two layers of the multiple layers of the plurality of layers of the second semiconductor chips are inconsistent" in combination with other elements of the base claims 9 and 13.
Claims 14-15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 9 and 14 that recite "etching the second-contact-pads after forming the second-contact-pads, so as to form voids between sidewalls of the second-contact-pads and sidewalls of the plurality of the through vias" in combination with other elements of the base claims 9 and 14.
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 17 that recite "the width of the first second-contact-pad is larger than a width of the first first-contact-pad or the first third-contact-pad corresponded thereto; the width of the second second-contact-pad is smaller than a width of the second first-contact-pad and the second third-contact-pad corresponded thereto" in combination with other elements of the base claims 1 and 17.
Claim 18 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 18 that recite "the width of the first second-contact-pad is larger than a width of the first first-contact-pad and the first third-contact-pad corresponded thereto; the width of the second second-contact-pad is smaller than a width of the second first-contact-pad or the second third-contact-pad corresponded thereto" in combination with other elements of the base claims 1 and 18.
Claim 19 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims because the prior art of record neither anticipates nor render obvious the limitations of the base claims 1 and 19 that recite "the width of the first second-contact-pad is larger than a width of the first first-contact-pad and the first third-contact-pad corresponded thereto; the width of the second second-contact-pad is smaller than a width of the second first-contact-pad and the second third-contact-pad corresponded thereto" in combination with other elements of the base claims 1 and 19.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to TONG-HO KIM whose telephone number is (571)270-0276. The examiner can normally be reached Monday thru Friday; 8:30 AM to 5PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Lynne Gurley can be reached at 571-272-1670. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/TONG-HO KIM/Primary Examiner, Art Unit 2811
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