Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed 11/19/2025 have been fully considered but they are not persuasive. Applicant argues that Jeon fails to teach the amended limitation to claim 1: “the first pulse high value is equal to the second pulse high value” on pages 6-8. Examiner respectfully disagrees. As discussed in the non-final rejection filed 08/25/2025, fig. 9B depicts signal UP/DN (writing leveling signal) and PWY (command path signal) having the equal high values. Further, fig. 10B shows that the UP/DN signal is generated via a D latch with PWY as its D input. From the Wikipedia page on Latches in digital circuits: “The D latch outputs the D input whenever the Enable line is high, otherwise the output is whatever the D input was when the Enable input was last high. This is why it is also known as a transparent latch - when Enable is asserted, the latch is said to be "transparent" - signals propagate directly through it as if it isn't there.” Therefore, the high value for UP/DN clearly must be equal to the high value for PWY.
Applicant further argues on pages 8 and 9 that Jeon fails to teach the newly amended limitation to claim 11: “a pulse in the writing leveling signal is ahead of a pulse in the command path signal.” While the examiner agrees that the UP/DN signal is indeed generated, and follows, the pulse of PWY, the examiner respectfully disagrees that this means Jeon does not teach “a pulse in the writing leveling signal is ahead of a pulse in the command path signal.” As depicted in fig. 11, steps 306 (detect phase difference between PWY and PDSP_p at memory device) and 308 (transmit feedback signal UP/DN to controller) is followed by step 312 (repeat for multiple devices in system), which is then followed by step 304 (generate internal pulsed write command signal PWY). Because the process is repeated multiple times, the first UP/DN (writing leveling signal) pulse is followed by the second PWY (command path signal) pulse.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Jeon (US Publication No. 20110047319).
Regarding claim 1, Jeon teaches:
A signal separation device, comprising:
a memory, (Fig. 1: Memory system 100) comprising:
a test circuit, configured to output a test signal; (Fig. 1, Memory controller 102 outputs a signal including: C/A, CLK, DQS. The signal is considered to be a test signal, and the controller is considered to be a test circuit because the application of the signal effectively tests Memory Device 105’s ability to perform writing leveling.)
a first buffer, configured to output a first delay signal according to the test signal; (Fig. 7: command buffer 202 receives outputs delayed signal CMD_b according to test signal including CMD)
a command terminal, configured to output a command path signal according to the test signal and the first delay signal; (Fig. 7: write command signal generator 210 (command terminal) outputs command path signal PWY according to CMD_d, based off of delayed signal CMD_b, which is based off of the test signal including CMD).
a writing terminal, configured to output a writing leveling signal according to the test signal and the first delay signal; (para. 94: During operation in the write leveling mode of operation, as determined by the state of the leveling enable signal leveling_en, the match and phase detector 216 detects a difference in phase between the write clock signal PWY [based on CMD_d which is based on first delay signal CMD_b] and the pulsed data strobe signal PDSD_p and generates an up/down UP/DN signal in response. Para. 63: The controller 102 can process the feedback signal 107, such as the UP/DN information, and make adjustments to the data strobe signal accordingly.)
wherein the first buffer is coupled between the test circuit and the command terminal; (Fig. 7, command buffer 202 (first buffer) is coupled between the test circuit (outputting signal CMD) and write command signal generator 210 (command terminal).
wherein the writing leveling signal comprises a first pulse signal, and the first pulse signal has a first pulse high value; (fig. 9B: UP/DN (writing leveling signal) represented as a pulse signal, having a first pulse high value represented by the amplitude of the pulse.)
wherein the command path signal comprises a second pulse signal, and the second pulse signal has a second pulse high value; (fig. 9B: PWY (command path signal) represented as a pulse signal, having a second pulse high value represented by the amplitude of the pulse).
wherein the first pulse high value is equal to the second pulse high value. (Fig. 9B: PWY and UP/DN are represented as having the same pulse amplitude. Also see fig. 10B: PWY as D input to D latch that generates UP/DN signal. When the UP/DN is high, it has the same pulse high value as PWY.)
Regarding claim 2, Jeon teaches the signal separation device of claim 1. Jeon further teaches:
wherein the memory further comprises a second buffer (Fig. 7: DQS Buffer (second buffer))
Regarding claim 3, Jeon teaches the signal separation device of claim 2. Jeon further teaches:
wherein the second buffer is configured to output a second delay signal according to the test signal. (Fig. 7: DQS Buffer 206 (second buffer) outputs a second delay signal (PDSD) according to the test signal including DQS).
Regarding claim 5, Jeon teaches the signal separation device of claim 3. Jeon further teaches:
wherein the second buffer is coupled between the test circuit and the writing terminal. (Fig. 7: DQS buffer (second buffer) is coupled between the test circuit (outputting signal DQS) and match and phase detector 216 (writing terminal)).
Regarding claim 7, Jeon teaches the signal separation device of claim 5. Jeon further teaches:
wherein a difference between the first pulse signal and the second pulse signal is N phase periods; wherein N is a positive integer greater than 0. (Fig. 9B: PWY and UP/DN are offset by some amount of time. Because a phase period is not a standardized amount of time and there is no limiting explicit definition in the instant application of a “phase period,” the BRI of N phase periods, where N is a positive integer greater than 0 is any nonzero amount of time.)
Regarding claim 8, Jeon teaches the signal separation device of claim 7. Jeon further teaches:
wherein the N phase periods are related to the first delay signal or/and the second delay signal. (Fig. 7: Feedback signal 107 (UP/DN) is based off of PDSD_P (based off of the second delay signal) and PWY (based off of the first delay signal), and thus can only be transmit upon having both. Therefore, the difference in time between PWY and UP/DN (the N phase periods) is related to the first and second delay signals.)
Regarding claim 9, Jeon teaches the signal separation device of claim 2. Jeon further teaches:
wherein the memory further comprises a first wire and a second wire; wherein the first wire is coupled between the test circuit and the command terminal; wherein the second wire coupled between the test circuit and the writing terminal. (fig. 7: first wire is considered to be from memory controller (test circuit) CMD -> Command Buffer 202 -> CMD-b -> Command Decoder 208 -> CMD_d -> Write Command Signal Generator (Command Terminal). Second wire is considered to be from memory controller (test circuit) DQS -> DQS Buffer 206 -> PDSD -> Internal DQS Gen 212 -> PDSD_P -> Match and Phase Detector 216 (writing terminal).)
Regarding claim 10, Jeon teaches the signal separation device of claim 9. Jeon further teaches:
wherein the first buffer is located on the first wire; wherein the second buffer is located on the second wire. (fig. 7: first wire is considered to be from memory controller (test circuit) CMD -> Command Buffer 202 (first buffer) -> CMD-b -> Command Decoder 208 -> CMD_d -> Write Command Signal Generator (Command Terminal). Second wire is considered to be from memory controller (test circuit) DQS -> DQS Buffer 206 (second buffer) -> PDSD -> Internal DQS Gen 212 -> PDSD_P -> Match and Phase Detector 216 (writing terminal).)
Regarding claim 11, Jeon teaches:
A signal separation method, comprising:
Outputting a test signal by a test circuit; (Fig. 1, Memory controller 102 outputs a signal including: C/A, CLK, DQS. The signal is considered to be a test signal, and the controller is considered to be a test circuit because the application of the signal effectively tests Memory Device 105’s ability to perform writing leveling.)
Outputting a first delay signal by a first buffer according to the test signal; (Fig. 7: command buffer 202 receives outputs delayed signal CMD_b according to test signal including CMD)
Outputting a command path signal by a command terminal according to the test signal and the first delay signal; (Fig. 7: write command signal generator 210 (command terminal) outputs command path signal PWY according to CMD_d, based off of delayed signal CMD_b, which is based off of the test signal including CMD).
wherein the first buffer is coupled between the test circuit and the command terminal; (Fig. 7, command buffer 202 (first buffer) is coupled between the test circuit (outputting signal CMD) and write command signal generator 210 (command terminal).
Outputting a writing leveling signal by a writing terminal according to the test signal and the first delay signal; (para. 94: During operation in the write leveling mode of operation, as determined by the state of the leveling enable signal leveling_en, the match and phase detector 216 detects a difference in phase between the write clock signal PWY [based on CMD_d which is based on first delay signal CMD_b] and the pulsed data strobe signal PDSD_p and generates an up/down UP/DN signal in response. Para. 63: The controller 102 can process the feedback signal 107, such as the UP/DN information, and make adjustments to the data strobe signal accordingly.)
wherein the writing leveling signal comprises a first pulse signal, and the first pulse signal has a first pulse high value; (fig. 9B: UP/DN (writing leveling signal) represented as a pulse signal, having a first pulse high value represented by the amplitude of the pulse.)
wherein a pulse in the writing leveling signal is ahead of a pulse in the command path signal. (fig. 11: steps 306 (detect phase difference between PWY and PDSP_p at memory device) and 308 (transmit feedback signal UP/DN to controller) is followed by step 312 (repeat for multiple devices in system), which is then followed by step 304 (generate internal pulsed write command signal PWY). Because the process is repeated multiple times, the first UP/DN (writing leveling signal) pulse is followed by the second PWY (command path signal) pulse.)
Claims 12, 13, 15, and 17-20 correspond to claims 2, 3, 5, and 7-10 (respectively), and are rejected accordingly.
Claim 16 corresponds to limitations contained in claim 1, and is rejected accordingly.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to JACK K BARNETT whose telephone number is (571)270-0431. The examiner can normally be reached M-Th 8-5, F 8-4 EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Mark Featherstone can be reached at 571-270-3750. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JACK KENSINGTON BARNETT/ Examiner, Art Unit 2111
/GUERRIER MERANT/ Primary Examiner, Art Unit 2111 1/12/2026
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