Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claims 1 and 7 have been objected for missing antecedent basis for claim language “…depositing an encapsulant over…… and lens”.
Similar correction is needed for claim 15.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 7-11 and 14 are rejected under 35 U.S.C. 102a (1) as being anticipated by Mitsukura (CN 103257527, hereinafter Mitsukura)
With respect to claim 7, Mitsukura discloses a method of making a semiconductor device (Fig. 34), comprising: providing a semiconductor die (12); depositing an adhesive over (1) the semiconductor die; disposing a lens (38) including a stepped edge over the semiconductor die (38 has a stepped edge); and depositing an encapsulant (42) over the semiconductor die and lens (42 is over 12 and 38).
With respect to claim 8, Mitsukura discloses wherein the stepped edge includes a sloped portion (Fig. 34 – stepped edge of lens 38 has a slopped edge).
With respect to claim 9, Mitsukura discloses wherein the stepped edge includes a plurality of steps (Fig. 34 – stepped edge of 38 has multiple steps).
With respect to claim 10, Mitsukura discloses depositing the
encapsulant with a top surface coplanar to a top surface of the lens (Fig. 34).
With respect to claim 11, Mitsukura discloses depositing the
encapsulant with a sloped surface (Fig. 34 – 42 has a sloped surface).
With respect to claim 14, Mitsukura discloses depositing the
encapsulant over the stepped edge of the lens (Fig. 34 – depositing 42 over stepped edge of 38).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the 20claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-5, 15-19 are rejected under 35 U.S.C. 103 as being unpatentable over Mitsukura in view of Han et al. (US 2015/0001562, hereinafter Han).
With respect to claim 1, Mitsukura discloses a method of making a semiconductor device (Fig. 34), comprising: providing a semiconductor die (12); depositing an adhesive over (1) the semiconductor die; disposing a lens (38) including a stepped edge over the semiconductor die (38 has a stepped edge), wherein the stepped edge covers a footprint of the adhesive (Fig. 34); and depositing an encapsulant (42) over the semiconductor die and lens (42 is over 12 and 38), wherein the encapsulant extends over the stepped edge of the lens (42 extends over the stepped edge of 38).
Mitsukura does not explicitly disclose that the stepped edge completely covers the footprint of the adhesive.
In an analogous art, Han discloses that the stepped edge (Fig. 1 - stepped edge of 180) completely covers the footprint of the adhesive (111). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Mitsukura’s method/system by having Han’s disclosure in order to align different components of a semiconductor device to achieve the optimal results.
With respect to claim 15, Mitsukura discloses a semiconductor device (Fig. 34), comprising: a semiconductor die (12); an adhesive deposited over (1) the semiconductor die; a lens (38) including a stepped edge over the semiconductor die (38 has a stepped edge), wherein the stepped edge covers a footprint of the adhesive (Fig. 34); and an encapsulant (42) deposited over the semiconductor die and lens (42 is over 12 and 38), wherein the encapsulant extends over the stepped edge of the lens (42 extends over the stepped edge of 38).
Mitsukura does not explicitly disclose that the stepped edge completely covers the footprint of the adhesive.
In an analogous art, Han discloses that the stepped edge (Fig. 1 - stepped edge of 180) completely covers the footprint of the adhesive (111). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Mitsukura’s method/system by having Han’s disclosure in order to align different components of a semiconductor device to achieve the optimal results.
With respect to claims 2 and 16, Mitsukura discloses wherein the stepped edge includes a sloped portion (Fig. 34 – stepped edge of lens 38 has a slopped edge).
With respect to claims 3 and 17, Mitsukura discloses wherein the stepped edge includes a plurality of steps (Fig. 34 – stepped edge of 38 has multiple steps).
With respect to claims 4 and 18, Mitsukura discloses depositing the
encapsulant with a top surface coplanar to a top surface of the lens (Fig. 34).
With respect to claims 5 and 19, Mitsukura discloses depositing the
encapsulant with a sloped surface (Fig. 34 – 42 has a sloped surface).
With respect to claim 13, Mitsukura does not explicitly disclose wherein the stepped edge completely covers a footprint of the adhesive.
In an analogous art, Han discloses that the stepped edge (Fig. 1 - stepped edge of 180) completely covers a footprint of the adhesive (111). It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Mitsukura’s method/system by having Han’s disclosure in order to align different components of a semiconductor device to achieve the optimal results.
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Mitsukura in view of Daeschner (CN 111063787, hereinafter Daeschner).
With respect to claim 12, Mitsukura does not explicitly disclose wherein an edge of a top surface of the lens is located between the adhesive and a photosensitive circuit of the semiconductor die in plan view.
In an analogous art, Daeschner discloses wherein an edge of a top surface of the lens is located between the adhesive and a photosensitive circuit of the semiconductor die in plan view (Fig. 2; Page 05, last Para; Page 07; Para 02; Page 09; Para 01 ).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Mitsukura’s method/system by having Daeschner’s disclosure in order to optimize the size of the semiconductor device.
Claims 6 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Mitsukura/Han in view of Daeschner.
With respect to claim 12, Mitsukura/Han does not explicitly disclose wherein an edge of a top surface of the lens is located between the adhesive and a photosensitive circuit of the semiconductor die in plan view.
In an analogous art, Daeschner discloses wherein an edge of a top surface of the lens is located between the adhesive and a photosensitive circuit of the semiconductor die in plan view (Fig. 2; Page 05, last Para; Page 07; Para 02; Page 09; Para 01 ).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Mitsukura/Han’s method/system by having Daeschner’s disclosure in order to optimize the size of the semiconductor device.
Conclusion
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/MOHAMMAD M CHOUDHRY/ Primary Examiner, Art Unit 2899
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