Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
This action is responsive to the application No. 18/747,852 filed on June 19, 2024.
Priority
3. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
4. Acknowledgement is made of Applicant’s Information Disclosure Statement (IDS) form PTO-1449. These IDS has been considered.
Specification
5. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: “Semiconductor Package Comprising Stacked Semiconductor Chips and Method for Manufacturing The Same”.
Claim Objections
6. Claims 16, 17, 19 are objected to because of the following informalities: In the following, the claims should be recited to avoid indefiniteness due to lack of antecedent basis, and/or smooth flow of claim languages/phrases:
16. (Currently Amended) A manufacturing method of a semiconductor package comprising:
forming through silicon vias within a semiconductor die, wherein the through silicon vias extend from a front side to a back side of a substrate of the semiconductor die;
forming ball-shaped bonding pads in first ends of the through silicon vias;
exposing the ball-shaped bonding pads by etching a back side surface of the substrate;
forming a first dielectric layer on the exposed ball-shaped bonding pads and the etched back side of the substrate;
performing a planarization process on the ball-shaped bonding pads and the first dielectric layer;
forming a second dielectric layer on the planarized ball-shaped bonding pads and the first dielectric layer;
forming a pattern on the second dielectric layer exposing an upper surface of the planarized ball-shaped bonding pads; and
etching the pattern on the second dielectric layer and performing a chamfering process on the first dielectric layer around the ball-shaped bonding pads.
17. (Currently Amended) The manufacturing method of claim 16, wherein:
etching the pattern of the second dielectric layer and performing the chamfering process on the first dielectric layer around the first bonding pads are simultaneously performed by a single etching process.
19. (Currently Amended) The manufacturing method of claim 16, wherein:
forming the pattern on the second dielectric layer comprises;
forming a photoresist pattern on the second dielectric layer; and
etching the second dielectric layer exposed by the photoresist pattern to expose the upper surface of the planarized ball-shaped bonding pads.
Appropriate corrections are needed.
Claim Rejections - 35 USC § 102
7. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
8. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
9. Claims 1, 5-13 are rejected under 35 U.S.C. 102(a)(1)/(a)(2) as being anticipated by Seo et al. (US 2023/0060360 A1).
Regarding independent claim 1, Seo et al. teaches a semiconductor package comprising (Fig. 1, para [0035]):
a first semiconductor die (200, para [0021]) including a back side bonding structure (295/290, para [0058]); and
a second semiconductor die (100, para [0021]) including a front side bonding structure (172/164, para [0058]) bonded to the back side bonding structure,
wherein the back side bonding structure (295/290) includes
a first dielectric layer (290, para [0058]); and
first bonding pads (295, para [0058]) passing through the first dielectric layer (290),
the front side bonding structure (172/164) includes
a second dielectric layer (164, para [0044]) bonded to the first dielectric layer (290, para [0058]); and
second bonding pads (172, para [0058]) with each second bonding pad bonded to a respective first bonding pad (295) and passing through the second dielectric layer (164), and
wherein the first dielectric layer (290) includes oblique edge (see Fig. 2A- see the annotated figure below) portions around the first bonding pads (295) at a surface facing the second dielectric layer (164).
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Regarding claim 5, Seo et al. teaches wherein (Fig. 1):
each first bonding pad (295) among the first bonding pads (295) extends to a corresponding oblique edge portion among the oblique edge portions.
Regarding claim 6, Seo et al. teaches wherein (Fig. 1):
the first dielectric layer (290) is directly bonded to the second dielectric layer (164).
Regarding claim 7, Seo et al. teaches wherein (Fig. 1):
the first dielectric layer (190 first back-side insulating film or 290 second back-side insulating film) and the second dielectric layer (164) each include silicon nitride (para [0044], [0054]).
Regarding claim 8, Seo et al. teaches wherein (Fig. 1):
each first bonding pad (295) among the first bonding pads (295) is directly bonded to a corresponding second bonding pad (172) among the second bonding pads (172).
Regarding independent claim 9, Seo et al. teaches a semiconductor package comprising (Fig. 1, para [0021]):
a first semiconductor die (200, para [0021]) and a second semiconductor die (100, para [0021]),
wherein the first semiconductor die (200) includes:
a first substrate (210, para [0058]);
through silicon vias (215, para [0058]) extending from a front side of the first substrate (210) to a back side of the first substrate (210); and
a back side bonding structure (295/290, para [0058]) positioned on the back side of the first substrate (210),
the second semiconductor die (100) includes:
a second substrate (110, para [0058]);
a wire layer (130, para [0035]) positioned on the front side of the second substrate (110); and
a front side bonding structure (172/164, para [0047]) positioned on the wire layer (130) and bonded to the back side bonding structure (295/290),
the back side bonding structure (295/290) includes:
a first dielectric layer (290, para [0058]); and
first bonding pads (295, para [0058]) passing through the first dielectric layer (290), wherein each first bonding pad of the first bonding pads (295) is in contact with a through silicon via (215, para [0058]) among the through silicon vias, and
the front side bonding structure (172/164) includes:
a second dielectric layer (164, para [0044]) bonded to the first dielectric layer (290); and
second bonding pads (172, para [0049]) with each second bonding pad bonded to a respective first bonding pad (295) and passing through the second dielectric layer (164), wherein the first dielectric layer (290) includes oblique edge (see Fig. 2A – see the annotated figure below) portions around the first bonding pads (295) at a surface facing the second dielectric layer (164).
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Regarding claim 10, Seo et al. teaches wherein (Fig. 1, para [0021]):
the front side bonding structure (172/164) further includes a third dielectric layer (156, para [0049]) under the second dielectric layer (164), and
the second bonding pads (172) passes through the third dielectric layer (156).
Regarding claim 11, Seo et al. teaches wherein (Fig. 1, para [0021]):
the first semiconductor die (200) is the same type (DRAM, para [0022]) of die as the second semiconductor die (100).
Regarding claim 12, Seo et al. teaches wherein (Fig. 1, para [0021]):
the first semiconductor die (200) and the second semiconductor die (100) are each a dynamic random access memory die (DRAM, para [0022]).
Regarding claim 13, Seo et al. teaches wherein (Fig. 1, para [0021]):
the first semiconductor die (200, considering DRAM) is a different type of die than the second semiconductor die (100, considering AP, see para [0022]).
Claim Rejections - 35 USC § 103
10. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
11. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
12. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
13. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
a. Determining the scope and contents of the prior art.
b. Ascertaining the differences between the prior art and the claims at issue.
c. Resolving the level of ordinary skill in the pertinent art.
d. Considering objective evidence present in the application indicating obviousness or non-obviousness.
14. Claims 2-3 are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al. (US 2023/0060360 A1) as applied to claim 1 above, and further in view of Mccarthy et al. (US 2012/0104604 A1).
Regarding claim 2, Seo et al. teaches all of the limitations of claim 1 from which this claim depends.
Seo et al. is explicitly silent of disclosing wherein, each oblique edge portion of the oblique edge portions is rounded.
Mccarthy et al. teaches wherein (Fig. 3), each oblique edge portion of the dielectric layer (327) of the oblique edge portions is rounded (see the annotated figure below).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Mccarthy et al., while forming the bonding structure between the semiconductor chips of Seo et al., in order to significantly lower the overall stress profile due to more dielectric material being between the bonding connector (para [0025]).
Regarding claim 3, Seo et al. teaches all of the limitations of claim 1 from which this claim depends.
Seo et al. is explicitly silent of disclosing wherein, each first bonding pad of the first bonding pads includes a rounded side.
Mccarthy et al. teaches wherein (Fig. 3), each first bonding pad of the first bonding pads (326) includes a rounded side (see the annotated figure below).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Mccarthy et al., while forming the bonding structure between the semiconductor chips of Seo et al., in order to significantly lower the overall stress profile due to more dielectric material being between the bonding connector, such as solder ball and RDL pad (para [0025]).
15. Claims 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Seo et al. (US 2023/0060360 A1) as applied to claim 13 above, and further in view of Jeng et al. (US 2018/0151512 A1).
Regarding claim 14, Seo et al. teaches all of the limitations of claim 13 from which this claim depends.
Seo et al. is explicitly silent of disclosing wherein, the first semiconductor die is a bottom die of a 3D integrated circuit, and the second semiconductor die is a top die of the 3D integrated circuit.
Jeng et al. teaches wherein (Fig. 1A, para [0015]), the first semiconductor die (112) is a bottom die of a 3D integrated circuit, and the second semiconductor die (118) is a top die of the 3D integrated circuit.
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Jeng et al., while forming the package structure of the stacked semiconductor chips of Seo et al., in order to achieve higher performance, smaller device size, and lower power.
Regarding claim 15, Seo et al. and Jeng et al. teach all of the limitations of claim 14 from which this claim depends.
Seo et al. is explicitly silent of disclosing wherein, the 3D integrated circuit comprises a system on chip (SoC).
Jeng et al. teaches wherein (Fig. 1A, para [0015]), the 3D integrated circuit comprises a system on chip (SoC) (para [0015]).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the invention to apply the teaching as taught by Jeng et al., while forming stacked semiconductor dies/chips of Seo et al., in order to obtain significantly higher energy efficiency, faster data processing and area-wise space saving.
Allowable Subject Matter
16. Claims 16-20 are allowed.
17. The following is an examiner’s statement of reasons for allowance:
Claim 16: the prior art of record alone or in combination neither teaches nor makes obvious a manufacturing method of a semiconductor package, comprising:
….
etching the pattern on the second dielectric layer and performing a chamfering process on the first dielectric layer around the ball-shaped bonding pads;
18. Claim 4 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4 recites…. further comprising:
air spaces,
wherein each air space of the air spaces is defined by the oblique edge portion of the first dielectric layer, the surface of the second dielectric layer facing the first dielectric layer, the surface of each second bonding pad facing the first dielectric layer among the second bonding pads, and the side of each first bonding pad among the first bonding pads.
19. None of the prior art of references indicated as the prior art made of record in form PTO-892, or found in the searches, disclose all the limitations of the independent claim 16 (the individual limitations may be found just not in combination) that recites the stacked semiconductor chips in a semiconductor package structure including bonding structure. Because no reference alone, nor is there any motivation to combine the details over the prior art to create such limitations in the independent claim 16.
Examiner’s Note
20. Applicant is reminded that the Examiner is entitled to give the broadest reasonable interpretation to the language of the claims. Furthermore, the Examiner is not limited to Applicants' definition which is not specifically set forth in the claims. See MPEP 2111, 2123, 2125, 2141.02 VI, and 2182.
Examiner has cited particular paragraphs and/or columns/lines in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner. See MPEP 2141.02 VI.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Conclusion
21. Any inquiry concerning this communication or earlier communications from the examiner should be directed to DIDARUL MAZUMDER whose telephone number is (571)272-8823. The examiner can normally be reached M-F 9-5.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
22. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William Partridge can be reached at 571-270-1402. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DIDARUL A MAZUMDER/Primary Examiner, Art Unit 2812
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