Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
The amendments filed on 4/20/206 have been fully considered and made of record in this application.
Response to Arguments
Applicant’s arguments with respect to claims 1, 16-18, and 21-36 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
This action is made final.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 31 and 36 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claims 31 and 36 recite the limitation " the non-solder interconnects " in line 1. There is insufficient antecedent basis for this limitation in the claim.
In claims 31 and 36, the phrase “ the non-solder interconnects “ is vague and indefinite since it is not clear from the claim where the non-solder interconnects are located.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
7. Claims 1, 16-18, 21-30, 32, 34 and 35 are rejected under 35 U.S.C. 103 as being unpatentable over Duan et al. (2024/0030065) in view of Kim et al. (US 20190096825) and Wang et al. (US 10,879,183).
With respect to Claims 1, 16, 28, and 34, Duan discloses a first metallization portion 1822 and a second metallization portion 1824. A first passive device 1834 located between the first metallization portion 1822 and the second metallization portion 1824, wherein the first passive device does not directly touch the second metallization portion. A first encapsulation layer 1854 located between the first metallization portion and the second metallization portion. A plurality of post interconnects 1852 located vertically between the first metallization portion and the second metallization . The plurality of post interconnects 1852 are coupled to and directly touch the first metallization portion and the second metallization portion. A first integrated device 1804 coupled to the first metallization portion 1822 . A second integrated device 1808 coupled to the first metallization portion (see paragraphs 142-151; Fig. 18).
Wangs fails to disclose a dummy silicon structure located laterally between the first integrated device and the second integrated device. The dummy silicon comprises a silicon back side surface that is co-planar with the first back side surface of the first integrated circuit. A second encapsulation layer coupled to the first metallization portion, wherein the second encapsulation layer at least partially encapsulates the first integrated device, the second integrated device and the dummy silicon structure. However, Duan a dummy silicon structure 131 located laterally between the first integrated device 122 and the second integrated device 123. The dummy silicon 131 comprises a silicon back side surface that is co-planar with the first back side surface of the first integrated circuit. A second encapsulation layer 110 coupled to the first metallization portion, wherein the second encapsulation layer at least partially encapsulates the first integrated device, the second integrated device and the dummy silicon structure (see Figs. 6 and 8-11). Thus, Wang and Duan have substantially the same environment of a plurality of chips encapsulated by a dielectric material that is mounted on an interconnect structure. Therefore, one skilled in the art before the effective filing date of the claimed invention to incorporate a dummy silicon structure between the plurality of chips of Wang, since the silicon structure would facilitate improving warpage characteristics of the overall semiconductor package as taught by Duan.
With respect to Claims 17, 30, 32, and 35, Duan discloses the first metallization portion 1822 comprises at least one first dielectric layer and a first plurality of metallization interconnects. The second metallization portion 1824 comprises at least one second dielectric layer and a second plurality of metallization interconnects. The plurality of post interconnects are coupled to and directly touch (i) the first
plurality of metallization interconnects and (ii) the second plurality of metallization
interconnects (see Fig. 18).
With respect to Claims 18 and 24, Duan and Kim disclose the claimed invention except for the passive device comprises a deep trench capacitor device. However, it is well known in the semiconductor industry to have a capacitor that is a deep trench capacitor device as evident by Wang (see col. 2 lines 35-40)
With respect to Claims 21 and 25, Duan discloses the passive device 1834 comprises a front side and a back side, wherein the front side of the passive device faces in a direction towards the first metallization portion 1822 (see Fig. 18).
With respect to Claims 22, Duan discloses the first encapsulation layer 1854 at
least partially encapsulates the first passive device (see Fig. 18).
With respect to Claims 23, Duan discloses the first encapsulation layer 1854 is
located vertically between the first metallization portion and the second metallization portion (see Fig. 18).
With respect to Claims 26, Duan discloses the back side of the first passive
Device 1834 faces in a direction towards the second metallization portion (see Fig. 18).
With respect to Claims 27, Duan discloses the first passive device 1834 vertically partially overlaps with the first integrated device (see Fig. 18).
With respect to Claim 29, Kim discloses the dummy silicon structure 131 is
free of any electrical connection with the first integrated device 122 and/or the second integrated device123 (see Fig. 19).
Allowable Subject Matter
8. Claims 33 are objected to as being dependent upon a rejected base
claim, but would be allowable if rewritten in independent form including all of the
limitations of the base claim and any intervening claims.
9. The following is a statement of reasons for the indication of allowance subject
matter: none of the prior art of record does not teaches or suggest the combination of the first metallization portion comprises at least one first dielectric layer and a first plurality of metallization interconnects. The second metallization portion comprises at least one second dielectric layer and a second plurality of metallization interconnects. The passive device comprises a front side and a back side, and
wherein (i) the front side of the passive device is coupled to the first plurality of
metallization interconnects through a first plurality of solder interconnects and/or (ii) the back side of the passive device is coupled to the second plurality of metallization interconnects through a second plurality of solder interconnects in claim 33.
The prior art made of record and not relied upon is cited primarily to show the
product of the instant invention.
Conclusion
10. THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time
policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE
MONTHS from the mailing date of this action. In the event a first reply is filed within
TWO MONTHS of the mailing date of this final action and the advisory action is not
mailed until after the end of the THREE-MONTH shortened statutory period, then the
shortened statutory period will expire on the date the advisory action is mailed, and any
nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be
calculated from the mailing date of the advisory action. In no event, however, will the
statutory period for reply expire later than SIX MONTHS from the mailing date of this
final action.
Any inquiry concerning the communication or earlier communications from the
examiner should be directed to Alonzo Chambliss whose telephone number is (571)
272-1927.
If attempts to reach the examiner by telephone are unsuccessful, the examiner's
supervisor, Jacob Y Choi can be reached on (469) 295-9060. The fax phone number for
the organization where this application or proceeding is assigned is (571) 273-8300.
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AC/June 29, 2026 /Alonzo Chambliss/
Primary Examiner, Art Unit 2897
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