DETAILED ACTION
This Office Action is in response to the continuation application filed on 20 June 2024.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 8 and 15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Uda (US 2019/0305129 A1; hereinafter Uda).
In regards to claim 8, Uda teaches, e.g. in fig. 2, an integrated chip, comprising:
a source region (18) and a drain region (20) in a substrate (12) [0031];
a shallow trench isolation (STI) structure (34) extending into the substrate [0031];
a gate electrode (28) over the substrate [0032]; and
a gate dielectric layer (26) separating the gate electrode from the substrate [0032],
wherein the gate electrode has a protrusion (42) directly between the source region and the drain region [0036], and wherein the protrusion protrudes into the STI structure beginning at a lower surface of the gate electrode, which is recessed relative to a top surface of the gate dielectric layer (fig. 2).
In regards to claim 15, Uda teaches the limitations discussed above in addressing claim 8. Uda further teaches, e.g. in fig. 2, the limitations wherein the source region, the drain region, the gate electrode, and the gate dielectric layer form a laterally-diffused metal-oxide semiconductor (LDMOS) transistor [0002].
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 16-18 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Uda, in view of Wu et al. (US 2016/0307911 A1; hereinafter Wu).
In regards to claim 16, Uda teaches, e.g. in fig. 2, a method, comprising:
forming a source region (18) and a drain region (20) in a substrate (12) [0031];
forming a trench isolation structure inset (34) into the substrate [0031]; and
forming a gate electrode (42) within the trench (fig. 2) [0036].
Uda appears to be silent as to, but does not preclude, the limitations of performing a first etch into the trench isolation structure to form a trench directly between the source region and the drain region; forming a mask structure over the trench isolation structure, wherein the mask structure has a mask opening that overlaps with the trench and that further overlaps with a top surface portion of the trench isolation structure outside the trench; and performing a second etch into the trench isolation structure through the mask opening to expand the trench. Wu teaches the limitations of performing a first etch into the trench isolation structure to form a trench directly between the source region and the drain region [0015-0016]; forming a mask structure over the trench isolation structure, wherein the mask structure has a mask opening that overlaps with the trench and that further overlaps with a top surface portion of the trench isolation structure outside the trench [0021]; and performing a second etch into the trench isolation structure through the mask opening to expand the trench [0015-0016]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Uda with the aforementioned limitations taught by Wu to have a desired etch profile (Wu [0016]).
In regards to claim 17, the combination of Uda and Wu teaches the limitations discussed above in addressing claim 16. Wu further teaches the limitations wherein the first etch is performed by a dry etch, and wherein the second etch is performed by a wet etch [0015-0016]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Uda with the aforementioned limitations taught by Wu to have a desired etch profile (Wu [0016]).
In regards to claim 18, the combination of Uda and Wu teaches the limitations discussed above in addressing claim 16. Wu further teaches the limitations wherein the mask opening has a width that is greater than a width of the trench [0021]. It would have been obvious to one having ordinary skill in the art at the time the application at hand was filed to modify the limitations taught by Uda with the aforementioned limitations taught by Wu to have a desired etch profile (Wu [0016]).
In regards to claim 20, the combination of Uda and Wu teaches the limitations discussed above in addressing claim 16. Uda further teaches the limitations further comprising:
depositing a conductive layer (28) overlying the substrate (12) and the trench isolation structure (34) and further filling the trench, wherein a top surface of the conductive layer is indented directly over the trench (fig. 2); and
patterning the conductive layer to form the gate electrode from a portion of the conductive layer (fig. 2).
Allowable Subject Matter
Claims 1-7 are allowed.
Claims 9-14 and 19 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The claims of the application at hand that depend from allowable claims (or objected to as being dependent upon a rejected base claim but would be allowable) are allowable (or objected to as being dependent upon a rejected base claim but would be allowable) because they respectively depend, directly or indirectly, from the allowable claims of the application at hand. Therefore, the dependent claims in question incorporate the allowable limitations of the claims from which they depend.
The following is a statement of reasons for the indication of allowable subject matter:
In regards to claim 1, Uda teaches, e.g. in fig. 2, an integrated chip, comprising:
a source region (18) and a drain region (20) in a substrate (12) [0031];
a trench isolation structure (34) inset into the substrate [0031];
a gate electrode (28/42) on the substrate, between the source region and the drain region (fig. 2) [0036]; and
a gate dielectric layer (26) separating the gate electrode from the substrate [0032],
wherein the gate electrode has a gate protrusion (42) that extends into the trench isolation structure, wherein the gate protrusion has a first sidewall (e.g. ending at (S2)) and a second sidewall (e.g. ending at (S1)) facing a common direction on a common side of the gate protrusion (fig. 2: e.g. left).
Uda and the closest prior art does not teach or disclose, alone or in combination, the limitations wherein the second sidewall is over the first sidewall and has a top edge farther from a width-wise center of the gate protrusion than a bottom edge of the second sidewall, and wherein first sidewall has a top edge farther from the width-wise center than a bottom edge of the first sidewall.
In regards to claims 9-14 and 19, the closest prior art does not teach or disclose, alone or in combination, the limitation wherein the bottom surface of a gate electrode is coplanar with the bottom surface of a gate dielectric, and further wherein the gate electrode is in physical contact with a top surface of a shallow trench isolation structure.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CALVIN Y CHOI whose telephone number is (571)270-7882. The examiner can normally be reached M-F 8-4 (Pacific Time).
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CALVIN CHOI
Patent Examiner
Art Unit 2812
/CALVIN Y CHOI/Patent Examiner, Art Unit 2812
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