DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claims 1-20 are pending and examined.
Priority
Acknowledgment is made of applicant's claim for foreign priority based on an application filed in Republic of Korea on 12/27/2023. It is noted, however, that applicant has not filed a certified copy of the KR10-2023-0193334 application as required by 37 CFR 1.55.
Paper filed on 05/27/2025 states that an attempt by the Office to electronically retrieve KR10-2023-0193334 application has failed on.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 11, 17 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over US 11,942,138 to Kim (hereafter Kim).
Regarding independent claim 1, Kim teaches a memory device, comprising:
a memory cell array including a plurality of memory cells (FIG. 1: memory cell aray 210); and
a refresh control circuit (FIG. 1: refresh control module 130) configured to generate a refresh row address and perform a refresh operation on memory cells of a row corresponding to the refresh row address (FIG. 1: row-hammer address RH_ADD),
wherein the refresh control circuit includes a row hammer managing circuit (RHMC) including:
a first row address generator (comprising latch LAT11, counter CNT1 of FIG. 4, setting circuit 352_1 and comparator CMP1 of FIG 6, adjacent address calculating circuit 3562 of FIG. 7) configured to receive first input row addresses (FIG. 4: receiving ACT_ADD at counter CNT1, which match with SAM_ADD1) during a first monitoring length (FIG. 6: PI<1> is generated in response to refresh rate N±1, see 9:50-63) and determine a first candidate address among the first input row addresses (FIG. 7: output of P_LAT1) based on a first reference address (FIG. 4: SAM_ADD1);
a second row address generator (comprising latch LAT12, counter CNT2 of FIG. 4, setting circuit 352_2 and comparator CMP2 of FIG 6, pipe latch P_LAT2 of FIG. 7) configured to receive second input row addresses (FIG. 4: receiving ACT_ADD at counter CNT2, which match with SAM_ADD2) during a second monitoring length longer than the first monitoring length (FIG. 6: PI<2> is generated in response to refresh rate N±2, see 9:50-63), and determine a second candidate address among the second input row addresses (FIG. 7: output of P_LAT12) based on a second reference address (FIG. 4: SAM_ADD2); and
a row address checker (FIG. 7: row-hammer address latch circuit 356) configured to determine the refresh row address based on the first candidate address and the second candidate address (FIG. 7: determining RH_ADD based on SAM_ADDx, which are seen comprising SAM_ADD1 and SAM_ADD2),
wherein the row corresponding to the refresh row address is adjacent to a row corresponding to an aggressor row address (FIG. 7: outputs of P_LAT1 and P_LAT2 are adjacent address(es) SAM_ADD_ADJ of an aggressor row address SAM_ADD1 or SAM_ADD2), and
wherein each of the first monitoring length and the second monitoring length is a cycle for performing the refresh operation (see 9:50-63).
Kim suggests determining adjacent row addresses using SAM_ADD1 and SAM_ADD2 via adjacent address calculating circuit 3562 of FIG. 7. The refresh row address is then determined using adjacent row addresses via pipe latch circuit 3564 of FIG. 7. In contrast, the present invention suggests determining an aggressor row address using SAM_ADD1 and SAM_ADD2. The refresh row address is subsequently determined using the aggressor row address.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that the two approaches suggested in Kim and present invention are functional equivalent because they yield the same output, i.e. target refresh row address, with same inputs, i.e. first and second candidate addresses SAM_ADD1 and SAM_ADD2.
Regarding dependent claim 2, Kim teaches wherein: the first row address generator is configured to transmit the first candidate address to the row address checker based on the first monitoring length as the cycle (FIG. 7: SAM_ADDx comprising SAM_ADD1 and corresponding PI<1> are inputs of row-hammer address latch circuit 356), the second row address generator is configured to transmit the second candidate address to the row address checker based on the second monitoring length as the cycle (FIG. 7: SAM_ADDx comprising SAM_ADD2 and corresponding PI<2> are inputs of row-hammer address latch circuit 356), and the row address checker is inherently configured to store at least one of the first candidate address and the second candidate address (in order to generated SAM_ADD_ADJ).
Regarding dependent claim 3, Kim teaches wherein: the row address checker is configured to implicitly compare the first candidate address at a first aggressor row refresh time (FIG. 7: such as enabling output of P_LAT1 in response to SAM_ADD_ADJ with timing PI<1> and PO<1>, wherein SAM_ADD_ADJ may corresponding to SAM_ADD1) with the second candidate address at a second aggressor row refresh time following the first aggressor row refresh time (FIG. 7: such as enabling output of P_LAT2 in response to SAM_ADD_ADJ with timing PI<2> and PO<1>, wherein SAM_ADD_ADJ may corresponding to SAM_ADD2), and determine the aggressor row address based on the comparison result (FIG. 7: whichever output presents on RH_ADD first).
Regarding dependent claim 11, Kim teaches a third row address generator (comprising latch LAT1m, counter CNTm of FIG. 4, setting circuit 352_k and comparator CMPk of FIG 6, pipe latch P_LATk of FIG. 7) configured to receive third input row addresses (FIG. 4: receiving ACT_ADD at counter CNTm, which match with SAM_ADDm) during a third monitoring length longer than the second monitoring length (FIG. 6: PI<k> is generated in response to refresh rate N±k, see 9:50-63), and determine a third candidate address (FIG. 7: output of P_LAT1m) among the third input row addresses based on a third reference address (FIG. 4: SAM_ADDx comprising SAM_ADDm), wherein the row address checker is configured to determine the refresh row address based on the first candidate address, the second candidate address, and the third candidate address.
Regarding dependent claim 17, Kim teaches wherein: the first monitoring length corresponds to an adjacent row of aggressor row refresh interval (i.e. for refresh rate of 1, see 9:46-63).
Regarding independent claim 19, Kim teaches a memory device, comprising:
a memory cell array including a plurality of memory cells (FIG. 1: memory cell aray 210); and
a refresh control circuit (FIG. 1: refresh control module 130) configured to:
generate candidate addresses based on a reference address (generating SAM_ADD_ADJ of FIG. 7, each corresponding to one of SAM_ADD1 and SAM_ADD2 of FIG. 4) and row addresses input (FIG. 4: ACT_ADD) during different monitoring lengths (refresh rates N±1 and N±2, see 9:50-63),
generate a refresh row address based on whether the candidate addresses match (FIG. 7: RH_ADD), and
output the refresh row addresses of rows adjacent to a row corresponding to an aggressor row address (FIG. 7: via adjacent address calculating circuit 3562),
wherein the memory device is configured to perform a refresh operation on memory cells of rows corresponding to the refresh row addresses (i.e. RH_ADD is the target refresh address), and
wherein each of the different monitoring lengths is a cycle for performing the refresh operation (see 9:50-63).
Kim suggests determining adjacent row addresses using SAM_ADD1 and SAM_ADD2 via adjacent address calculating circuit 3562 of FIG. 7. The refresh row address is then determined using adjacent row addresses via pipe latch circuit 3564 of FIG. 7. In contrast, the present invention suggests determining an aggressor row address using SAM_ADD1 and SAM_ADD2. The refresh row address is subsequently determined using the aggressor row address.
It would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to realize that the two approaches suggested in Kim and present invention are functional equivalent because they yield the same output, i.e. target refresh row address, with same inputs, i.e. first and second candidate addresses SAM_ADD1 and SAM_ADD2.
Allowable Subject Matter
Claims 4-10, 12-16, 18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 20 is allowed.
The following is a statement of reasons for the indication of allowance:
The prior art made of record and considered pertinent to the applicant's disclosure does not teach or suggest the claimed invention having the following limitations, in combination with the remaining claimed limitations.
With respect to dependent claim 4: wherein: the row hammer managing device is configured such that the row address checker determines the first candidate address at the second aggressor row refresh time as the aggressor row address when the first candidate address at the first aggressor row refresh time matches the second candidate address at the second aggressor row refresh time.
With respect to dependent claim 5: wherein: the row hammer managing device is configured such that the row address checker changes the second reference address to the first candidate address at the second aggressor row refresh time when the first candidate address at the first aggressor row refresh time matches the second candidate address at the second aggressor row refresh time.
With respect to dependent claim 6: wherein: the row hammer managing device is configured such that the row address checker determines the second candidate address at the second aggressor row refresh time as the aggressor row address when the first candidate address at the first aggressor row refresh time does not match the second candidate address at the second aggressor row refresh time.
With respect to dependent claim 7: wherein: the row hammer managing device is configured such that the row address checker changes the first reference address to the second candidate address at the second aggressor row refresh time when the first candidate address at the first aggressor row refresh time does not match the second candidate address at the second aggressor row refresh time.
With respect to dependent claims 8-10: wherein: the second row address generator is configured to monitor the second input row addresses during the second monitoring length from the first aggressor row refresh time, the row hammer managing device further includes a third row address generator configured to determine a third candidate address by monitoring third input row addresses during the second monitoring length from the second aggressor row refresh time following the first aggressor row refresh time, and the row address checker is configured to determine the aggressor row address based on the first candidate address and one of the second candidate address and the third candidate address.
With respect to dependent claims 12-15: wherein: the row address checker is configured to compare the first candidate address at a first time and the second candidate address at a second time, and compare the second candidate address at a third time and the third candidate address at the second time.
With respect to dependent claim 16: wherein: the first monitoring length corresponds to an aggressor row refresh interval, and the third monitoring length corresponds to 'aggressor row refresh interval*4'.
With respect to dependent claim 18: wherein: the second monitoring length corresponds to 'aggressor row refresh interval*2'.
With respect to independent claim 20: modifying the reference address based on the comparison result.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to VANTHU NGUYEN whose telephone number is (571)272-1881. The examiner can normally be reached M-F: 7:00AM - 3:00PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Richard Elms can be reached at (571) 272-1869. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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December 5, 2025
/VANTHU T NGUYEN/Primary Examiner, Art Unit 2824