DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of claims 1-14 in the reply filed on 8/10/2026 is acknowledged.
Claims 15-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected method claims, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 8/10/2026.
Allowable Subject Matter
Claim 14 is allowed.
The following is an examiner’s statement of reasons for allowance:
Regarding Claim 14, prior art failed to disclose or fairly suggest a semiconductor package comprising, along with other recited claim limitations,
wherein the third chip pad of a second semiconductor chip, of the plurality of second semiconductor chips, disposed at a lowermost side of the chip structure and the second chip pad of the first semiconductor chip are coupled to each other, and a second insulating layer of the second semiconductor chip that is disposed at the lowermost side of the chip structure and the first insulating layer of the first semiconductor chip are coupled to each other, wherein a third chip pad of a second semiconductor chip, of the plurality of second semiconductor chips, that is disposed at an uppermost side of the chip structure and the fourth chip pad of the third semiconductor chip are coupled to each other, and a third insulating layer of the second semiconductor chip that is disposed at the uppermost side of the chip structure and the fourth insulating layer of the third semiconductor chip are coupled to each other, wherein the first substrate has a first width and a first thickness, wherein the second substrate has a second width and a second thickness, and the third substrate has a third width and a third thickness, wherein the third thickness is thicker than the second thickness, and the third width is greater than the second width, and the third thickness is thicker than the first thickness, and the third width is smaller than the first width.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-13 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Uzoh et al. (2020/0411483).
Regarding Claim 1, in Fig. 4, Uzoh et al. discloses a semiconductor package comprising: a first semiconductor chip 104 (see paragraph 0035 where substrate 104 could be a die) including a first substrate and a first through electrode passing through the first substrate, wherein the first substrate has a first active (bottom/back) surface and a first non-active (top/front) surface; a chip structure including a plurality of second semiconductor chips 102/102’/102’’/102’’’ stacked on the first semiconductor chip, wherein each second semiconductor chip includes a second substrate and a second through electrode passing through the second substrate, wherein the second substrate has a second active surface and a second non-active surface; and a third semiconductor chip 106’ disposed on the chip structure, and including a third substrate having a third active (bottom/back) surface and a third non-active (top/front) surface, wherein the first substrate has a first width and a first thickness, wherein the second substrate has a second width and a second thickness, and the third substrate has a third width and a third thickness, wherein the third thickness is thicker than the second thickness, and the third width is greater than the second width (see paragraphs 0003, 0005, 0031, 0044, 0049, 0051 and 0091 and particularly the thickness/width/dimension of the die in relationship to the hybrid/direct bonding issues such as warpage/deformation)
Regarding Claim 2, the third thickness (of top die 106) is thicker than the first thickness (of element 104), and the third width (of element 106) is smaller than the first width (of 104).
Regarding Claim 3, an edge of the third semiconductor chip 106 protrudes farther in a horizontal direction than a corresponding edge of a second semiconductor chip 102/102’/102’’/102’’’, of the plurality of second semiconductor chips, disposed at an uppermost side of the chip structure.
Regarding Claim 4, a distance between the edge of the third semiconductor chip and the corresponding edge of the second semiconductor chip that is disposed at the uppermost side of the chip structure is about 20 micrometers or more (one can take any distance since the presence of “a” in the limitation)
Regarding Claim 5, wherein the plurality of second semiconductor chips 102/102’/102’’/102’’’ and the third semiconductor chip 106 are memory chips.
Regarding Claim 6, a remaining scribe line region of the third semiconductor chip 106 is wider than a remaining scribe line region of the second semiconductor chip 102/102’/102’’/102’’’ (this is inherently so).
Regarding Claim 7, the third substrate 1046 includes silicon, and the third thickness is about 150 micrometers or more.
Regarding Claim 8, the second semiconductor chip 102/102’/102’’/102’’’ is a memory chip, and the third semiconductor chip 106 is a dummy chip.
Regarding Claim 9, a chip pad of a second semiconductor chip, of the plurality of second semiconductor chips, that is disposed at a lowermost side of the chip structure and a chip pad of the first semiconductor chip are coupled to each other, and an insulating layer, which is adjacent to the chip pad of the second semiconductor chip that is disposed at the lowermost side of the chip structure, and an insulating layer, which is adjacent to the chip pad of the first semiconductor chip, are coupled to each other (see paragraphs 0035, 0055, 0093, 0101).
Regarding Claim 10, chip pads of the plurality of second semiconductor chips 102/102’/102’’/102’’’ face each other in the chip structure and are coupled to each other, and insulating layers that are adjacent to the chip pads of the second semiconductor chip face each other and are coupled to each other (see paragraphs 0035, 0055, 0093, 0101)
Regarding Claim 11, each of the second active surface (of elements 102/102’/102’’/102’’’) and the third active surface face (of element 106) toward the first semiconductor chip 104.
Regarding Claim 12, each of the second non-active surface (of elements 102/102’/102’’/102’’) and the third active surface (of element 106) faced toward the first semiconductor chip 104 (the structure could be in flipped orientation).
Regarding Claim 13, a mold layer (1404 in Fig. 14 or 2014 in Fig. 20)at least partially surrounding a side of the chip structure 102/102’/102’’/102’’’ and a side of the third semiconductor chip 104 and exposing a side of the first semiconductor chip 104 and an upper surface of the third semiconductor chip 106.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to FAZLI ERDEM whose telephone number is (571)272-1914. The examiner can normally be reached M-F, 8am-5pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Davienne Monbleau can be reached at 571-272-1945. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/FAZLI ERDEM/Primary Examiner, Art Unit 2812 10/6/2026
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