DETAILED ACTION
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 06/20/2024 is filed after the mailing date of the application. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-3, 8, 15, 17, 20 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Hsu et al., U.S. Pub. No. 2020/0243464.
Regarding claim 1, Hsu discloses a semiconductor controller, comprising (Fig. 6):
a substrate 100,
a controller semiconductor die 101 (SoC) physically and electrically mounted to the substrate 100 (101 connect to substrate),
a thermal interface material (TIM) layer (fig. 6: high thermal conductive 104 + heat dissipating 105) comprising first and second opposed surfaces, the first surface of the TIM layer affixed to a surface of the controller semiconductor die (bottom surface of high thermal conductive DAF 104 is adhered to top surface of chip 101), the TIM layer configured to conduct heat away from the controller semiconductor die (thermal conductivity, 105 is expressly a heat dissipating element), and
an encapsulant for at least partially encapsulating the semiconductor controller (figs. 4, 6: molding compound 500 encapsulates dies 101 and heat-dissipating element 105), wherein the second surface of the TIM layer is exposed through the encapsulant (figs. 4, 106: upper surface 105a is exposed to air and flush with the upper surface of molding compound 500).
Regarding claim 2, Hsu discloses wherein the controller semiconductor die is flip-chip [0055] mounted to the substrate by a plurality of solder balls 1011 (Fig. 4, 6).
Regarding claim 3, Hsu discloses wherein the TIM layer is comprised of a plurality of sublayers (104+105).
Regarding claim 8, Hsu discloses the encapsulant forms a border around at least one side of the exposed surface of the TIM layer (Fig. 4).
Regarding claim 9, Hsu discloses the exposed second surface of the TIM layer forms the entire upper surface of the semiconductor controller (Fig. 4).
Regarding claim 15, Hsu discloses a semiconductor controller, comprising (Figs. 4, Fig. 6):
a substrate 100,
one or more semiconductor memory dies 103 physically and electrically coupled to the first substrate 100interconnections to base 100), and
a semiconductor controller for controlling operation of the one or more semiconductor memory dies (SoC semiconductor chip 101), the semiconductor controller comprising:
a second substrate 100,
a controller semiconductor die 103 physically and electrically mounted to the second substrate,
a thermal interface material (TIM) layer (figs. 4, 6: high thermal conductive 104 + heat dissipating 105) comprising first and second opposed surfaces, the first surface of the TIM layer affixed to a surface of the controller semiconductor die (bottom surface of high thermal conductive DAF 104 is adhered to top surface of chip 103), the TIM layer configured to conduct heat away from the controller semiconductor die (thermal conductivity, 105 is expressly a heat dissipating element), and
an encapsulant for at least partially encapsulating the semiconductor controller (figs. 4, 6: molding compound 500 encapsulates dies 101, 103 and heat-dissipating element 105), wherein the second surface of the TIM layer is exposed through the encapsulant (figs. 4, 6: upper surface 105a is exposed to air and flush with the upper surface of molding compound 500).
Regarding claim 17, Hsu discloses wherein the TIM layer is comprised of a plurality of sublayers of different materials (104+105).
Regarding claim 18, Hsu discloses wherein the encapsulant is applied to the controller die after the TIM layer is directly affixed to the controller die (Fig. 6).
Regarding claim 19, Hsu discloses the encapsulant forms a border around at least one side of the exposed surface of the TIM layer (Fig. 4).
Regarding claim 20, Hsu discloses a semiconductor controller 5b, comprising (Fig. 4, Fig. 6):
a substrate 100,
a controller semiconductor die 101 physically and electrically mounted to the substrate,
thermal interface means, connected to the controller semiconductor die (104+105), for conducting heat away from the controller semiconductor die 101, and an encapsulant 500 for at least partially encapsulating the semiconductor controller, wherein a portion of the thermal interface means is exposed through the encapsulant (top surface 105a exposed through molding compound 500).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 4-7, 12-14 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al., U.S. Pub. No. 2020/0243464, in view of Chang et al., U.S. Pub. No. 2025/0118615.
Regarding claim 4, Hsu fails to disclose the first sublayer of TIM layer comprises copper. Chang discloses the first TIM 170 (Fig. 4A) layer comprises of copper [0038]-[0039].
It would have been obvious to one of ordinary skill in the art to modify the TIM layer of Hsu to comprise copper, as taught by Chang, in order to provide increased thermal conductivity and thereby improve heat dissipation from the semiconductor die.
Regarding claim 5, Hsu discloses the controller of claim 4, wherein a second sublayer of the TIM layer 105 is comprised of one of a thermally conductive adhesive and a thermally conductive solder mask [0057].
Regarding claim 6, Hsu and Chang fail to disclose a third sublayer and a fourth sublayer of the TIM layer. It would have been obvious to one having ordinary skill in the art at the time the invention was made to modify the TIM layer of Hsu to include additional sublayers by repeating the known layered structure, since the mere duplication of known layers performing the same known function would have been an obvious modification absent a new or unexpected result. In re Harza, 274 F.2d 669, 671 (CCPA 1960).
Still regarding claim 6, Hsu and Chang fail to disclose the third sublayer comprises Ni and the fourth sublayer is Cr. It would have been obvious to one having ordinary skill in the art at the time the invention was made to have the third layer is Ni and fourth layer is Cr, because Ni and Cr were well known conductive materials conventionally used in multilayer structures, and selection of such known materials for their known properties would have yielded predictable results, which is to provide increased thermal conductivity and thereby improve heat dissipation from the semiconductor die.
Regarding claim 7, Hsu and Chang disclose the encapsulant is applied to the die after the TIM layer is affixed to the controller die.
Regarding claim 12, Chang discloses wherein the TIM layer is singulated from the panel with the controller semiconductor die [0132].
Regarding claims 13-14, Chang discloses wherein the controller is an ASIC [0073], or a specialized processor comprising one of a graphics processing unit and an artificial intelligence processing unit [0073].
Claims 10, 11 are rejected under 35 U.S.C. 103 as being unpatentable over Hsu et al., U.S. Pub. No. 2020/0243464, in view of Yang et al., U.S. Pub. No. 20180269181.
Regarding claim 10, Hsu fails to disclose wherein the encapsulant is mold compound applied using a pair of mold plates. Yang discloses wherein the encapsulant is mold compound applied using a pair of mold plates 200a and 200b [0044].
It would have been obvious to one having ordinary skill in the art at the time the invention was made to apply the encapsulant of Hsu using a pair of mold plates comprising a bottom mold plate 200a and a top mold plate 200b, as taught by Yang, in order to define a mold cavity for receiving the encapsulant during the molding process.
Regarding claim 11, Yang discloses the controller is one of a plurality of controllers formed on a panel wherein the TIM layer is applied as a sheet over all of the controllers on the panel (Figs. 1-3).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THAO P LE whose telephone number is (571)272-1785. The examiner can normally be reached on Monday-Friday 9AM-6PM.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jeff Natalini can be reached on 571-272-2266. The fax phone number for the organization where this application or proceeding is assigned is 703-872-9306.
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/THAO P LE/Primary Examiner, Art Unit 2818
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