Prosecution Insights
Last updated: October 02, 2026
Application No. 18/748,530

CAPACITOR AND SEMICONDUCTOR DEVICE AND ELECTRONIC DEVICE

Non-Final OA §102§103
Filed
Jun 20, 2024
Priority
Dec 04, 2023 — RE 10-2023-0173786
Examiner
KIM, SU C
Art Unit
Tech Center
Assignee
Samsung Electronics Co., Ltd.
OA Round
1 (Non-Final)
78%
Grant Probability
Favorable
1-2
OA Rounds
6m
Est. Remaining
66%
With Interview

Examiner Intelligence

Grants 78% — above average
78%
Career Allowance Rate
718 granted / 923 resolved
+17.8% vs TC avg
Minimal -12% lift
Without
With
+-11.8%
Interview Lift
resolved cases with interview
Typical timeline
2y 9m
Avg Prosecution
35 currently pending
Career history
962
Total Applications
across all art units

Statute-Specific Performance

§101
0.2%
-39.8% vs TC avg
§103
59.5%
+19.5% vs TC avg
§102
23.8%
-16.2% vs TC avg
§112
6.4%
-33.6% vs TC avg
Black line = Tech Center average estimate • Based on career data from 923 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1-13 & 19-21 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Malhotra et al. (US 20130122681). Regarding claim 1, Malhotra discloses that a capacitor 300, comprising: a first electrode 302 comprising a topological material (para. 0035), a second electrode 306 & 308 facing the first electrode, and a dielectric film 304 between the first electrode and the second electrode. Reclaim 2, Malhotra discloses that the first electrode comprises: a first conductive layer comprising a conductor, and a second conductive layer comprising the topological material, wherein the conductor and the topological material are different in chemical composition (para. 0035 & 0040-0041, note: “- -or combinations thereof”). Reclaim 3, Malhotra discloses that the conductor included in the first conductive layer comprises a metal oxide (para. 0035 & 0040-0041). Reclaim 4, Malhotra discloses that the conductor included in the first conductive layer comprises molybdenum oxide (para. 0035 & 0040-0041). Reclaim 5, Malhotra discloses that the topological material and the metal oxide comprise at least one same metal element (para. 0035 & 0040-0041). Reclaim 6, Malhotra discloses that the topological material and the metal oxide each comprise molybdenum (para. 0035 & 0041). Reclaim 7, Malhotra discloses that the metal oxide comprises a molybdenum oxide of the formula MoOx wherein 2≤x≤3, and the topological material comprises MoP, MoN, MoC, MoTe2, MoSTe, MoSi₂, MoSeTe, Mo(1-z)WzTe₂ wherein 0<z≤1, or a combination thereof (para. 0035 & 0041). Reclaim 8, Malhotra discloses that a first surface of the second conductive layer 302 (can be multi layers in para. 0035) is in contact with the dielectric film 304, and an opposite second surface of the second conductive layer is in contact with the first conductive layer (para. 0035 & 0041). Reclaim 9, Malhotra discloses that the dielectric film comprises a dielectric material which is a product of epitaxial growth on the first surface of the second conductive layer having a dielectric constant that is greater than a dielectric constant of silicon oxide ((para. 0038, note: some of dielectric has a constat greater than a dielectric constant of silicon oxide, i.e. HfO2 BST et.). Reclaim 10, Malhotra discloses that the topological material comprises MoP, MoN, MoC, MoTe2, MoSTe, MoSi₂, MoSeTe, Mo(1-z)W≥Te₂ wherein 0<z≤1, or a combination thereof, and the dielectric comprises TePb, PbSe, PbS, Bi2Te3, TiO₂, Bi2Se3, LiNbO₃, LiTaO₃, Ge(Bi₃O₅)₄, LaAIO₃, CeO2, Ge, InSb, GaSb, NdGaO₃, ZrO₂, TeO2, InP, GaAs, YAIO₃, Te₂Mo, CdWO4, or a combination thereof (para. 0035 & 0040-0041). Reclaim 11, Malhotra discloses that the first electrode further comprises a third conductive layer spaced apart from the second conductive layer, the third conductive layer disposed on a surface of the first conductive layer (para. 0035). Reclaim 12, Malhotra discloses that the third conductive layer comprises the topological material, Ti, TiN, TiON, or a combination thereof (para. 0035). Regarding claim 13, Malhotra discloses that a semiconductor device comprising: a semiconductor substrate, a transistor, wherein the transistor is integrated into the semiconductor substrate or disposed on the semiconductor substrate, and the capacitor of claim 1, the capacitor being electrically connected to the transistor 502 (Fig. 5). Regarding claim 19, Malhotra discloses that an electronic device comprising the capacitor of claim 1. Reclaim 20, Malhotra discloses that an electronic device comprising the semiconductor device of claim 13 (Fig. 5, para. 0035 & 0040-0041). Regarding claim 21, Malhotra discloses that a method of manufacturing a capacitor 520, the method comprising: depositing a conductor on a substrate 501 to form a first conductive layer 504; disposing a second conductive layer (para. 0035, can be multi layers) on the first conductive layer to form a first electrode; disposing a dielectric film 506 on the first electrode, wherein the second conductive layer 506 is disposed between the dielectric film and the first conductive layer to form a composite; and disposing a second electrode on the composite, wherein the dielectric film is disposed between the first electrode and the second electrode to manufacture the capacitor (para. 0040-0041, can be multi layers), wherein the second conductive layer comprises a topological material, the first conductive layer comprises a metal oxide, and the topological material and the metal oxide comprise at least one same metal element (para. 0040-0041). Claim(s) 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US 20050161726). Regarding claim 14, Shin discloses that a semiconductor device comprising: a semiconductor substrate 50, a transistor 54, wherein the transistor is integrated into the semiconductor substrate or disposed on the semiconductor substrate (Fig. 2), and a capacitor C electrically connected to the transistor and comprising a first electrode 43, a dielectric film 44, and a second electrode 49, wherein the first electrode comprises a first conductive layer comprising a first conductor, and a second conductive layer in contact with the dielectric film, and a second conductor of a different chemical composition than the first conductor, and wherein the first conductor and the second conductor comprise at least one same metal element (para. 0067, 40-Ir electrode and 42-IrO.x). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim(s) 15-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US 20050161726) in view of Malhotra et al. (US 20130122681). Reclaim 15, Shin fails to specify that a resistivity of the first electrode is less than a resistivity of the first conductive layer. However, Malhotra suggests that a resistivity of the first electrode is less than a resistivity of the first conductive layer (0035 & 0040-0041, can combine). Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Shin with a resistivity of the first electrode is less than a resistivity of the first conductive layer as taught by Malhotra in order to enhance assisting in lowering the leakage current (para. 0034) and also, the claim would have been obvious because the substitution of one know element for another would have yielded predictable results to one of ordinary skill in the art at the time of the invention. Reclaim 16, Shin & Malhotra disclose that the first conductor comprises a molybdenum oxide of the formula MoOx wherein 2≤x≤3, and the second conductor comprises MoP, MoN, MoC, MoTe₂, MoSTe, MoSi2, MoSeTe, Mo(1-z)WzTe₂ wherein 0<z≤1, or a combination thereof (para. 0035 & 0040-0041). Reclaim 17, Shin & Malhotra disclose that the first electrode further comprises a third conductive layer disposed on a surface of the first conductive layer and comprising the topological material, Ti, TiN, TiON, or a combination thereof (Shin in view of Malhotra’s para. 0035 & 0040-0041). Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Shin et al. (US 20050161726) in view of Malhotra et al. (US 20130122681) and further in view of Kweon et al.(US 20030047771). Reclaim 18, Shin & Malhotra disclose that an interlayer insulating film on the transistor (Shin, Fig. 2). Shin & Malhotra fails to teach that the capacitor is formed in a trench in the interlayer insulating film. However, Kweon suggests that capacitor 81, 62, 63 is formed in a trench in the interlayer insulating film 80 (Fig. 4). Therefore, it would have been obvious to one of ordinary skill in the art before effective filing date of applicant(s) claimed invention was made to provide Shin & Malhotra with the capacitor is formed in a trench in the interlayer insulating film as taught by Kweon in order to enhance variation of shapes and also, the claim would have been obvious because a particular know technique was recognized as part of the ordinary capabilities of one skilled in the art. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to SU C KIM whose telephone number is (571)272-5972. The examiner can normally be reached M-F 9:00 to 5:00. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Dale Page can be reached at 571-270-7877. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /SU C KIM/ Primary Examiner, Art Unit 2899
Read full office action

Prosecution Timeline

Jun 20, 2024
Application Filed
Sep 18, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
78%
Grant Probability
66%
With Interview (-11.8%)
2y 9m (~6m remaining)
Median Time to Grant
Low
PTA Risk
Based on 923 resolved cases by this examiner. Grant probability derived from career allowance rate.

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