DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 05/21/2025 and 06/20/2024 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 17 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over Calder et al. (US 2020/0182983 A1) in view of Koifman et al. (US 2018/0372873 A1).
Regarding claim 17, Calder discloses an image sensor pixel (Fig. 4) comprising:
a light-sensing diode (215);
an analog counter (455) coupled to a cathode terminal of the light-sensing diode and having an integration capacitor (Fig. 4 and par. [0056]);
a comparator (460) having an input coupled to the analog counter (Fig. 4 and par. [0056]).
Calder does not disclose an analog memory circuit coupled to an output of the comparator and having a plurality of memory capacitors smaller than the integration capacitor. Koifman, in the same field of endeavor, teaches an alternative method in which the output of a comparator may be either registered by a digital memory circuit or an analog memory circuit (42) comprising a plurality of conventional integrators (see Koifman, Fig. 5 and par. [0086]-[0087]. It is further noted that conventional integrators mentioned by Koifman encompass conventional capacitors, each is inherently smaller than the integration capacitor in order for the device to function effectively as an individual register cell).
Therefore, it would have been obvious to one of ordinary skill in the art to modify the image sensor taught by Calder to implement the alternative configuration in view of Koifman to arrive at the instant claimed feature for improved operation efficiency.
Regarding claim 18, the combination of Calder and Hoifman clearly discloses that the light-sensing diode comprises a single-photon avalanche diode (SPAD) (see Calder, par. [0043], [0056]).
Allowable Subject Matter
Claims 1-16 are allowed.
Claims 19 and 20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Regarding independent claim 1, the prior art references of record, either alone or in combination, fail to teach: “an analog counter coupled to a cathode terminal of the SPAD; and a comparator having a first input coupled to a floating diffusion node in the analog counter, a second input configured to receive a reference voltage, and a clock input configured to receive a comparator clock signal from the analog counter.”
Regarding independent claim 11, the prior art references of record, either alone or in combination, also fail to teach or suggest: “with an analog counter, adjusting an integration voltage at an integration capacitor by a step size and pulsing a comparator clock signal in response to detecting the photon; and with a comparator, receiving the comparator clock signal from the analog counter and comparing the integration voltage with a reference voltage in response to detecting an edge in the comparator clock signal.”
Regarding claim 19, the prior art references of record also fail to teach or suggest: “the analog counter comprises: a voltage-controlled pulse generator; a logic gate coupled between the cathode terminal of the light-sensing diode and an input of the voltage-controlled pulse generator; a charge pump coupled between an output of the voltage-controlled pulse generator and the integration capacitor; and a precharge transistor configured to precharge the integration capacitor.” Regarding claim 20, the prior art references of record also fail to teach or suggest: “the analog memory circuit further comprises: a read enable switch coupled between the output of the comparator and a storage node of the analog memory circuit; a first switch coupled between the storage node and a first memory capacitor in the plurality of memory capacitors; a second switch coupled between the storage node and a second memory capacitor in the plurality of memory capacitors; a third switch coupled between the storage node and a third memory capacitor in the plurality of memory capacitors; and a logic gate having a first input coupled to a first node disposed between the first switch and the first memory capacitor, a second input coupled to a second node disposed between the second switch and the second memory capacitor, a third input coupled to a third node disposed between the third switch and the third memory capacitor, and an output coupled to a quench transistor coupled to the cathode terminal of the light-sensing diode.”
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
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/NHAN T TRAN/Primary Examiner, Art Unit 2638