Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 06/03/2026 has been entered.
Response to Arguments
Applicant’s arguments with respect to claim(s) 1, 20 and 21 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument. Pauker at fig. 2 discloses an impedance-matching microstrip network (an intermediating circuit board) for matching a predetermined impedance to a lower impedance over a wide frequency band having a tapered line section for transposing the predetermined impedance to a higher impedance. At least one quarter wave line section is coupled to the narrow end of the tapered line section for transposing the higher impedance to the lower impedance.
Prior Art
Please note: Examiner has cited particular columns, line numbers, and figures in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teaching of the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. Applicants are reminded that MPEP 2141.02 states: A prior art reference must be considered in its entirety, i.e., as a whole, including portions that would lead away from the claimed invention. W.L. Gore & Associates, Inc. V. Garlock, Inc., 721 F.2d 1540, 220 USPQ 303 (Fed. Cir. 1983), cert. denied, 469 U.S. 851 (1984).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-5, 14-16 and 20-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida et al. (US 2004/0212381) hereafter Yoshida in view of Mahoney et al. (US 7,083,428 B1) hereafter Mahoney, Hsu et al. (US 6,552,696 B1), hereafter Hsu and Pauker (US 4,283,694).
Regarding claims 1-2 and 16, Yoshida throughout the disclosure particularly at fig. 1B, 3A, 5C discloses a test probe assembly with hybrid shielding sockets useful for testing a packaged integrated circuit (IC) device under test (DUT) [IC], the test probe assembly comprising: a main block 2 having a plurality of main probe retention cavities [“contact probes 1 inserted in respective insertion holes 21 of a metal block 2”] for housing a plurality of compressible probes 1 to connect between a plurality of DUT contacts [47a as an example] and a plurality of testing contacts [contacts of wiring board 5]; an upper block 8 having a plurality of upper probe cavities [cavities in 8 for 11 as shown] for housing an upper portion [11 as an example] of each of the plurality of compressible probes, wherein each of the plurality of compressible probes comprises an extending upper probe tip [portion of 11 as an example] that extends from the upper block to make contact with a DUT contact [fig. 7B] , wherein the upper block is made entirely [see fig. 3A for 8] from a non-conductive material (polyimide for claim 16); a lower block [¶0068, see “An insulative film may be provided on the metal cover 24 as in the upper portion of the metal block 2”] having a plurality of lower probe cavities [cavities for 12 e.g. 24a/24b as shown] for housing a plurality of lower probe tips [12 as an example] of the plurality of compressible probes. Yoshida disclose an intermediating circuit board 5 coupled to the plurality of lower probe tips [as shown].
Yoshida is silent about said non-conductive material is for impedance tuning between the DUT and a PCB test circuit, wherein the non-conductive material includes recesses for a ball grid array of the DUT, and wherein the upper block has a dielectric constant configured to provide impedance tuning; and said intermediating circuit board comprising a tapered conductor that transitions from a lower impedance to a higher impedance across a length of the tapered conductor.
Yoshida implicitly discloses capacitance between one or more of the extending upper probe tips 11 and the main block 2 i.e. Yoshida discloses said non-conductive material configured to provide impedance tuning [“impedance tuning” is product by process limitation, “[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985)] between the test probe assembly and the DUT.
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Use of the non-conductive material of upper block includes tapered recesses for a ball grid array of the DUT is old and well known in the art to guide the ball for stable contact with the probe and to support the ball for the probe. Mahoney in similar environment discloses a test probe assembly at fig. 5-6, the non-conductive material [“Substrate 370 is a substantially flat plate formed from an electrically insulating material, and defines an upper surface 372 and a lower surface 373”] of upper block 370,380 includes tapered recesses [376A-1, 376A-2 as shown, also see Abstract] for a ball grid array 101/102 of the DUT 100A. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify the recesses of Yoshida with tapered recesses as taught by Mahoney to guide the ball for stable contact with probe (see “each solder ball of BGA IC 100A becomes engaged with an associated chamfer of a corresponding through hole 376, thereby providing "fine" alignment of BGA IC 100A relative to contact springs 350. In particular, BGA IC 100A becomes engaged such that high-speed solder balls 101 become engaged with through-holes 376A-1, and low-speed solder balls 102 become engaged with through-holes 376A-2.”) and to support the ball for the probe during testing (see Abstract).
Use of the non-conductive material for impedance matching/tuning is old and well known in the art for enhancing signal transmission and power transfer efficiency. Yoshida, as said earlier, discloses non-conductive material 8 between the test probe assembly [fig. 5C] and the DUT 47. Yoshida at ¶0010-0011 discloses achieving a predetermined impedance by the coaxial structure (the test probe assembly) to prevent the influence of noise during high frequency operation (see Abstract). Yoshida also at ¶0055 also discloses “… predetermined impedance on the basis of … a dielectric constant of a dielectric substance interposed between the insertion hole 21 and the contact probe 1.” Hsu discloses non-conductive material (variable dielectric constant material) 20 configured to provide impedance tuning based on a capacitance (see Abstract) between electrodes/plates 12 and 22 to adjust the resonant frequency of the surface (see Abstract). Hsu also discloses “In another aspect the present invention provides a method of tuning a high impedance surface for a radio frequency signal. The method includes arranging a plurality of generally spaced-apart planar conductive surfaces in an array disposed essentially parallel to and spaced from a conductive back plane, the size of each conductive surface being less than a wavelength of the radio frequency signal and the spacing of each conductive surface from the back plane being less than a wavelength of the radio frequency signal; and varying the capacitance between adjacent conductive surfaces by locally varying a dielectric constant of a dielectric material to thereby tune the impedance of said high impedance surface.” Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to use non-conductive material for impedance matching as further taught by modified Yoshida and Hsu to take advantage of the impedance tuning.
Pauker disclose the intermediating circuit board 22 comprising a tapered conductor 25 that transitions from a lower impedance to a higher impedance across a length of the tapered conductor [see “ to provide an impedance-matching network wherein these drawbacks are obviated, which is suitable for use at a higher operating frequency or over a wider band and which has a predetermined, desired translated output impedance over the wide frequency band. … The impedance-matching network according to the invention is therefore characterized in that the predetermined impedance is converted into a higher impedance by means of the tapered line section and in that this higher impedance is converted into the lower impedance by means of at least a 1/4.lambda. line section. “]. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify board 5 of Yoshida with teaching of Pauker in order to obtain advantages that Pauker has to offer.
Therefore, the combination of Yoshida, Mahoney and Hsu and Pauker discloses all the elements of claims 1-2 and 16.
Regarding claim 3, Yoshida throughout the disclosure particularly at fig. 1B, 3A, 5C discloses the test probe assembly of claim 1 wherein the lower block is made from a non-conductive material [¶0068, see “An insulative film may be provided on the metal cover 24 as in the upper portion of the metal block 2”] for impedance tuning between the DUT and the PCB test circuit.
Regarding claim 4, Yoshida throughout the disclosure particularly at fig. 1B, 3A, 5C discloses the test probe assembly of claim 1 wherein the lower block includes [for lower 37] chamfered recesses [24a/24b] for housing and centering a plurality of lower ends of each probe barrel of the plurality of compressible probes 1.
Regarding claim 5, Yoshida throughout the disclosure particularly at fig. 1B, 3A, 5C discloses the test probe assembly of claim 1 wherein the plurality of main probe retention cavities of the main block include chamfers [for 37 as shown] for housing and centering a plurality of upper ends of each probe barrel [as shown] of the plurality of compressible probes 1.
Regarding claim 14, Yoshida throughout the disclosure particularly at fig. 1B, 3A, 5C discloses the test probe assembly of claim 1 wherein the main block includes an upper insulating spacer [upper 37] for retention of each probe barrel and wherein the dielectric constant and dimensions of the upper insulating spacer are selected to provide a capacitance characteristic suitable for impedance tuning between the test probe assembly and the DUT [¶0082-0085, see “the influence of impedance mismatch can be inhibited without involvement of an increase in the diameter of the insulative spacer”].
Regarding claim 15, Yoshida throughout the disclosure particularly at fig. 1B, 3A, 5C discloses the test probe assembly of claim 1 wherein the lower block 24 includes a lower insulating spacer [lower 37, as shown] for retention of each probe barrel and wherein the dielectric constant and dimensions of the lower insulating spacer are selected to provide a capacitance profile suitable for impedance tuning between the test probe assembly and the DUT [¶0082-0085, see “the influence of impedance mismatch can be inhibited without involvement of an increase in the diameter of the insulative spacer”].
Regarding claim 20, as explained above for rejection of claim1, the combination of Yoshida, Mahoney and Hsu and Pauker discloses all the elements of a system comprising: a main block comprising a plurality of main probe retention cavities for housing a plurality of compressible probes to connect between a plurality of device under test (DUT) contacts and a plurality of testing contacts; an upper block comprising a plurality of upper probe cavities for housing an upper portion of each of the plurality of compressible probes, wherein each of the plurality of compressible probes comprises an extending upper probe tip that extends from the upper block to make contact with a DUT contact, wherein the upper block is made entirely from a non-conductive material comprising a dielectric constant configured to provide impedance tuning based on a capacitance between the main block and the extending upper probe tip of each of the plurality of compressible probes, a lower block having a plurality of lower probe cavities for housing a lower portion of each of the plurality of compressible probes; and an intermediating circuit board coupled to lower probe tips of the plurality of compressible probes, the intermediating circuit board comprising a tapered conductor that transitions from a lower impedance to a higher impedance across a length of the tapered conductor.
Regarding claim 21, as explained above for rejection of claim 1, the combination of Yoshida, Mahoney and Hsu and Pauker discloses all the elements of a method comprising: providing a main block comprising a plurality of main probe retention cavities for housing a plurality of compressible probes; positioning an upper block relative to an upper portion of the main block, the upper block comprising a plurality of upper probe cavities for housing an upper portion of each of the plurality of compressible probes, wherein each of the plurality of compressible probes comprises an extending upper probe tip that extends from the upper block to make contact with a device under test (DUT) contact, wherein the upper block is made entirely from a non-conductive material comprising a dielectric constant configured to provide impedance tuning based on a capacitance between the main block and the extending upper probe tip of each of the plurality of compressible probes, positioning a lower block relative to a lower portion of the main block, the lower block comprising a plurality of lower probe cavities for housing a lower portion of each of the plurality of compressible probes; and coupling an intermediating circuit board to lower probe tips of the plurality of compressible probes, the intermediating circuit board comprising a tapered conductor that transitions from a lower impedance to a higher impedance across a length of the tapered conductor.
Claim(s) 6, 8-9, 12 and 17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida, Mahoney, Hsu and Pauker as applied to claim 1 above, and further in view of Kawate et al. (WO 2012/106221 A1), hereafter Kawate.
Regrading claim 6, modified Yoshida, particularly Yoshida discloses all the elements including an interposing pad [interposing pad (not shown) of 5] and a test probe assembly having a plurality of compressible probes 1 configured to repeatedly maintain reliable electrical contact with a corresponding plurality of DUT [IC 47 as an example]. Modified Yoshida is silent about said interposing pad having: a power layer and a ground layer insulated from each other; at least one signal layer insulated from the power layer and the ground layer, the at least one signal layer having one or more signal transmission lines; and one or more vias providing electrical coupling between a plurality of probes and the one or more signal transmission lines, and wherein the one or more vias are configured for transmitting and receiving signals from the DUT to at least one point of termination for cabling from a test equipment. Kawate at fig. 2 and 5 discloses a test probe assembly 1 having a plurality of compressible probes 4 configured to repeatedly maintain reliable electrical contact with a corresponding plurality of DUT [IC device] and an interposing pad 230 having: a power layer 2112 and a ground layer 2113 insulated 2111 from each other; at least one signal layer 2391 insulated 2110 from the power layer and the ground layer, the at least one signal layer having one or more signal transmission lines 2391/2392; and one or more vias 2383/2383 providing electrical coupling between a plurality of probes 2141/2146 and the one or more signal transmission lines 2391/2392, and wherein the one or more vias are configured for transmitting and receiving signals from the DUT [IC device] to at least one point of termination [2241/2244] for cabling from a test equipment. Therefore, it would have been obvious to a person having ordinary skill in the art to modify the PCB of modified Yoshida with interposing pad 230 as taught by Kawate, in order to provide impedance matching to maximize signal power transfer.
Regarding claim 8, Kawate at fig. 2 and 5 discloses the test probe assembly of claim 6 wherein the interposing pad includes two or more substrate materials [2110 made of glass epoxy resin or the like (e.g. paper, glass fiber) and dielectric polymer2111/2114 (as shown) and 2311/2314 (as described)] having different relative permittivities [see “to increase the capacitance of the condenser, preferably the dielectric constant of the dielectric layer 2111 is high, for example, preferably the dielectric layer 2111 is made from a high dielectric material having a dielectric constant greater than the dielectric constant of the base member 2110”].
Regarding claim 9, Kawate at fig. 2 and 5 discloses the test probe assembly of claim 8 wherein the two or more substrate materials are coupled using an anisotropic conductive film [ground layers 2116/2113 as shown and 2316/2313 as described] to provide electrical connectivity between the DUT and the at least one point of termination.
Regarding claim 12, Kawate at fig. 2 and 5 discloses the test probe assembly of claim 10 wherein an effect at a predetermined resonant frequency is enhanced depending upon a location of the resonator along the one or more signal transmission lines [2391/2392 as strip line, Pauker discloses the same].
Regarding claim 17, Kawate at fig. 2 and 5 discloses the test probe assembly of claim 1 wherein the intermediating circuit board includes one or more reactive elements incorporated into two impedance matching networks configured to match the lower impedance to the higher impedance, the one or more reactive elements comprising the tapered conductor. [controlling the impedance for quality and efficient transfer of a signal i.e. “by adjusting the value of each of the parameters in Equation (1), impedance matching can be carried out in the third substrate 230, and impedance matching between the circuit board and the pin holder 1 may be carried out.” Pauker at fig. 2 and Abstract discloses “An impedance-matching microstrip network for matching a predetermined impedance to a lower impedance over a wide frequency band having a tapered line section for transposing the predetermined impedance to a higher impedance. At least one quarter wave line section is coupled to the narrow end of the tapered line section for transposing the higher impedance to the lower impedance.”].
Claim(s) 10-11, 13 and 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida, Mahoney, Hsu, Pauker and Kawate as applied to claim 6 above, and further in view of Treibergs et al. (US 2015/0369840 A1), hereafter Treibergs.
Regarding claim 10, the combination of Yoshida, Mahoney, Hsu, Pauker and Kawate discloses all the elements of a test probe assembly of claim 6. They are silent about wherein the intermediating circuit board includes a coupled resonator and is formed at least by removing conductor material in a ground plane. Treibergs at fig. 7-10, ¶0040, ¶0044 discloses impedance controlled microwave structures (such as coplanar waveguide) therefore discloses the resonator is a coupled resonator 170/150 and is formed in a ground plane 140. Therefore, it would have been obvious to a person having ordinary skill in the art before the effective filing date to modify the resonator of the modified Yoshida with teaching from Treibergs to obtain same advantages that impedance matching has to offer and taught by the Treibergs. Regarding said coupled resonator is formed at least by removing conductor material in a ground plane, where removing conductor material is product by process limitation [“[E]ven though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process.” In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985)].
Regarding claim 11, Treibergs discloses the test probe assembly of claim 10 wherein the resonator comprises a circular segment etched [170 etch into 140] into the ground plane so as to present an open or short circuit effect at one of the one or more signal transmission lines for suppression or passage of a predetermined resonant frequency [¶0042].
Regarding claim 13, Treibergs discloses the test probe assembly of claim 10 wherein the ground plane is segmented [fig. 7, ¶0042].
Regarding claim 19, Modified Yoshida, particularly Pauker at fig. 2 disclose the one or more reactive elements 25 includes a wider line coupled to a narrower line to form a stepped transformer 15/18, wherein the wider line is associated with the lower impedance and the narrower line is associated with the higher impedance.
Claim(s) 18 is/are rejected under 35 U.S.C. 103 as being unpatentable over Yoshida, Mahoney, Hsu, Pauker and Kawate as applied to claim 17 above, and further in view of Ishikawa et al. (US 6169301 B) hereafter Ishikawa.
Regarding claim 18, the combination of Yoshida, Mahoney, Hsu, Pauker and Kawate discloses all the limitations. Pauker discloses tapered conductor. They are silent about one of the one or more reactive elements includes a stub protruding laterally from the tapered conductor. Ishikawa at fig. 5 discloses an impedance matching section/circuit with a tapered slot line 12 and stub S having appropriate length to obtain easy impedance matching. Therefore, it would have obvious to a person having ordinary skill in the art before the effective filing date add stub as taught by Ishikawa to modify the modified Yoshida in order to obtain advantages that Ishikawa has to offer i.e. easy impedance matching (see “An object of the present invention is to provide a planar dielectric integrated circuit such that energy conversion loss between the planar dielectric line and electronic components is small, and impedance matching between them is obtained easily.”).
Conclusion
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/PARESH PATEL/Primary Examiner, Art Unit 2858
June 13, 2026
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